Senior DFT Engineer (ATPG, MBIST, IO Test, Clock Verification)

Job Title

Senior DFT Engineer (ATPG, MBIST, IO Test, Clock Verification)

Role Summary

Design and deliver DFT solutions for high-performance GPU and SoC designs, focusing on scan-based DFT, ATPG, MBIST, IO test, and clock verification to improve test coverage, yield, and silicon reliability. Work closely with RTL, physical design, verification, and product teams to enable first-time-right silicon and production ramps.

Experience Level

Senior — requires 4+ years of hands-on DFT and ATPG experience as specified in the posting.

Responsibilities

Primary responsibilities include architecture, implementation, validation, and production support for DFT and test features.

• Architect and validate DFT solutions to improve controllability and observability in complex GPU/SoC designs.
• Lead scan insertion, compression, and integration of test logic.
• Generate, debug, and analyze ATPG patterns for stuck-at, transition, and additional fault models.
• Design and support MBIST architectures for on-chip memory test and diagnosis.
• Plan and validate IO tests for interface and pin-level reliability.
• Implement clock DFT and perform clock verification to enable at-speed testing.
• Analyze fault coverage reports and drive improvements while balancing power, performance, and area.
• Support pattern simulation, silicon bring-up, manufacturing test debug, yield ramp, and root-cause analysis.
• Document DFT methodologies, test strategies, and best practices aligned with quality standards.

Requirements

Must-have technical skills and experience.

• 4+ years of hands-on DFT and ATPG experience for SoC or ASIC designs.
• Strong understanding of DFT fundamentals: controllability, observability, and scan-based testing.
• Proven expertise in ATPG pattern generation, analysis, and debug.
• Experience with MBIST architectures and memory diagnostics.
• Experience with IO test methodologies for interface and pin-level validation.
• Knowledge of clock DFT and clock verification concepts.
• Solid digital design and RTL fundamentals.
• Experience with industry-standard DFT/ATPG EDA tools.
• Strong analytical, problem-solving, and communication skills; able to work effectively in fast-paced semiconductor programs.

Education Requirements

Preferred: B.Tech or BE in Electronics or a related domain (or equivalent degree). The posting also accepts equivalent practical experience.

About the Company

Company: E-Space

Headquarters: Saratoga, CA, United States

E-Space develops low Earth orbit (LEO) satellite systems to enable hyper-scaled Internet of Things (IoT) connectivity. The company designs advanced satellite hardware and communication systems to reduce costs, improve scalability, and deliver actionable intelligence from space.