Senior DfT Engineer

Job Title

Senior DfT Engineer

Role Summary

Design for Test (DfT) engineer responsible for defining and implementing testability features for complex mixed-signal and digital SoC designs. The role partners with product, analog/digital design, test, validation and quality teams to deliver DfT architecture, RTL, verification and silicon debug support.

Experience Level

Senior level. Seeking candidates with approximately 3–8 years of relevant experience; minimum 3 years in a DfT, digital design or architecture role.

Responsibilities

Primary responsibilities include designing, verifying and supporting DfT features across the product lifecycle.

• Collaborate with Product Definer, Analog/Digital Design Leads, Test, Product and Validation engineers to collect testability requirements (functional, debug, ATPG).
• Design and insert DfT for analog, mixed-signal IP and digital logic, including RAM/ROM/NVM and data converters.
• Develop high-quality RTL using Verilog and SystemVerilog.
• Define verification plans, write tests, debug and close issues in chip-top DV environments.
• Perform scan insertion, optimization, length balancing, test-point insertion and P&R-aware rerouting of chains.
• Generate ATPG patterns, run simulations and debug failing vectors.
• Support test engineers during silicon bring-up and on customer returns.
• Participate in design and test reviews and provide DfT recommendations.
• Create and maintain comprehensive DfT architecture and design documentation.
• Troubleshoot and resolve DfT-related issues throughout development; stay current with industry tools and methodologies.

Requirements

Must-have technical skills and constraints for the role.

• 3+ years of hands-on experience in DfT, digital design or architecture (seeking 3–8 years total experience).
• Proficient in RTL design and verification using Verilog and SystemVerilog.
• Practical experience with scan insertion, optimization, test-point insertion and ATPG pattern generation.
• Experience debugging ATPG patterns and supporting silicon bring-up and test engineering.
• Experience defining verification plans and working in chip-top DV environments.
• Strong problem-solving, teamwork, planning, organization, attention to detail and communication skills.
• Willingness to relocate to the Phoenix metro area and ability to be onsite in the Chandler office a minimum of three full days per week.

Nice-to-have:

• Experience with analog and mixed-signal IPs and standard macros (RAM, ROM, NVM, ADC, DAC).
• Experience with P&R-aware rerouting of scan chains and advanced physical-awareness during DfT insertion.
• Experience producing and maintaining formal DfT documentation and supporting customer returns.

Education Requirements

Master's degree (MSEE) with majority of coursework relevant to Digital Design, RTL coding, DfT, Computer Architecture or Digital Verification.

NXP is an Equal Opportunity/Affirmative Action Employer and provides reasonable accommodations for qualified individuals with disabilities.

About the Company

Company: NXP Semiconductors

Headquarters: Nijmegen, Netherlands

NXP Semiconductors N.V. is a global semiconductor company that provides High Performance Mixed Signal and Standard Product solutions. With over 45,000 employees and operations in more than 35 countries, NXP is a leader in secure connectivity solutions for embedded applications, catering to automotive, industrial IoT, mobile, and communication infrastructure markets. The company is committed to innovation and sustainability, advancing a smarter, safer, and more sustainable world through technology.