Senior DFT Engineer

Job Title

Senior DFT Engineer

Role Summary

Lead the definition and implementation of SoC DFT architecture and drive end-to-end DFT implementation from architecture through RTL integration, synthesis, and silicon bring-up. Work closely with RTL, physical design, verification, product engineering, and test teams to ensure testability, timing closure, and production test readiness.

Experience Level

Senior — typically 5–7 years of experience in DFT, ASIC, or SoC design and test-related roles.

Responsibilities

Primary responsibilities include architecture, implementation, verification, and production test support for SoC DFT solutions.

• Define and implement SoC DFT architecture: Scan, MBIST, LBIST, JTAG, Boundary Scan, and Test Compression.
• Drive end-to-end DFT implementation from architecture definition through RTL integration, synthesis, and silicon bring-up.
• Develop and validate scan insertion, scan chain stitching, test point insertion, and ATPG pattern generation to meet fault coverage targets.
• Perform RTL and gate-level DFT verification and debug DFT issues to ensure design testability.
• Implement and optimize Memory BIST (MBIST) and Logic BIST (LBIST) for complex SoCs.
• Collaborate with cross-functional teams to integrate DFT with physical design and achieve timing/DFT closure.
• Support ATPG pattern validation, ATE bring-up, silicon debug, and production test qualification.
• Optimize test coverage, pattern count, test power, and test execution time; maintain DFT specifications and documentation.
• Drive improvements in DFT methodologies, automation flows, and best practices.

Requirements

Must-have technical skills and experience for the role.

• 5–7 years of hands-on DFT experience in ASIC/SoC projects (experience requirement kept here for role clarity).
• Strong expertise in Scan, MBIST, LBIST, JTAG, Boundary Scan, and Test Compression methodologies.
• Hands-on experience with DFT/ATPG tools such as Siemens Tessent, Synopsys TestMAX/TetraMAX, or Cadence Modus.
• Solid understanding of ATPG concepts, fault modeling, and defect coverage analysis (stuck-at, transition, path-delay).
• Experience with RTL design and verification using Verilog and SystemVerilog.
• Understanding of low-power DFT methodologies and UPF/CPF-based flows.
• Experience with scan chain optimization, test point insertion, and DFT timing closure; familiarity with physical design constraints.
• Experience supporting silicon bring-up, ATE debug, and production test activities.

Nice-to-have:

• Exposure to mixed-signal DFT, memory test, and high-speed interface testing.
• Experience with SoC-level DFT architecture for large, complex designs and test compression expertise.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Microelectronics, VLSI, or a related field.

About the Company

Company: NXP Semiconductors

Headquarters: Nijmegen, Netherlands

NXP Semiconductors N.V. is a global semiconductor company that provides High Performance Mixed Signal and Standard Product solutions. With over 45,000 employees and operations in more than 35 countries, NXP is a leader in secure connectivity solutions for embedded applications, catering to automotive, industrial IoT, mobile, and communication infrastructure markets. The company is committed to innovation and sustainability, advancing a smarter, safer, and more sustainable world through technology.