Senior DFT Engineer

Job Title

Senior DFT Engineer

Role Summary

Join the SoC design team to define and implement Design-for-Test (DFT) strategies across complex digital SoCs targeting 5G, IoT, and LEO satellite communications. You will drive testability from early design through manufacturing test and collaborate with physical design and ATE teams to ensure silicon quality.

Work in a technical, mission-driven environment focused on scalable satellite connectivity systems.

Experience Level

Senior — minimum 8+ years of hands-on DFT experience for complex digital ASICs or SoCs.

Responsibilities

Implement and verify DFT architecture, own ATPG and test development, and integrate DFT into the overall implementation flow.

• Define and implement end-to-end DFT architecture and strategy (scan, MBIST, BIST, JTAG/IEEE 1149.x).
• Insert and verify scan chains, compression logic, and test wrappers using industry-standard DFT tools.
• Own the full ATPG lifecycle: verification, coverage analysis, pattern generation, and ATE bring-up.
• Perform fault simulation and analyze test coverage metrics to meet manufacturing requirements.
• Collaborate with physical design teams to optimize scan chain ordering, routing, and test timing.
• Define and implement MBIST and LBIST strategies for embedded memories.
• Work with ATE teams to develop test programs and validate tester compatibility.
• Develop DFT automation scripts and integrate DFT flows into the design implementation flow.
• Perform DFT sign-off verification and resolve DRC/functional issues related to DFT logic.
• Document DFT specifications, methodology guidelines, and test coverage reports.

Requirements

Key technical skills and practical experience required. Education requirements are listed separately below.

Must-have:

• Minimum 8+ years hands-on DFT experience for complex digital ASICs or SoCs.
• Hands-on experience with industry DFT tools (e.g., Synopsys DFT Compiler, Mentor/Siemens Tessent, or equivalent).
• Expertise in scan insertion, ATPG pattern generation (stuck-at, transition, IDDQ), and fault simulation.
• Experience with compression architectures (EDT, DFTMAX) and advanced DFT techniques.
• Working knowledge of MBIST architectures and embedded memory test strategies.
• Familiarity with JTAG/IEEE 1149.1, IEEE 1500, and IEEE 1687 (iJTAG) standards.
• Proficiency in scripting for automation and analysis (Tcl, Python, Perl).
• Experience collaborating with physical design and STA teams for scan chain closure and test timing.
• Strong understanding of digital design fundamentals and RTL design practices.
• Demonstrated ability to mentor engineers and scale technical practices across a team.

Nice-to-have:

• Experience with IEEE P1838 (3D-IC test) or die-to-die interface test methodologies.
• Exposure to at-speed test methodologies, on-chip clock control for at-speed test, and diagnosis flows for yield improvement.
• Experience with system-level test, in-system test (IST), and ATE platforms (Advantest, Teradyne).
• Experience using programming languages and AI tools to automate test flows.
• Background in satellite communications, 5G NR, or IoT SoC designs.

Education Requirements

MS or PhD in Electrical Engineering or a related field, or equivalent practical experience. (The posting explicitly accepts equivalent experience in lieu of the listed graduate degrees.)

About the Company

Company: E-Space

Headquarters: Saratoga, CA, United States

E-Space develops low Earth orbit (LEO) satellite systems to enable hyper-scaled Internet of Things (IoT) connectivity. The company designs advanced satellite hardware and communication systems to reduce costs, improve scalability, and deliver actionable intelligence from space.