Senior DFT Engineer

Job Title

Senior DFT Engineer

Role Summary

Design-for-Test (DFT) engineer responsible for implementing and verifying DFT solutions across hierarchical SoC/ASIC designs to achieve first-pass silicon success. The role works within the SoC/ASIC DFT development team and partners with physical design and ATE test teams to deliver test strategies and production-ready pattern files.

Experience Level

Senior - requires hands-on DFT experience. Minimum ~3 years experience in DFT design and verification; 5+ years preferred for more advanced responsibilities.

Responsibilities

Primary responsibilities include DFT architecture, insertion, verification, and production support across block and top levels.

• Develop and implement hierarchical DFT architectures for SoC and ASIC designs, including block-level and top-level integration.
• Perform scan insertion, test point insertion, and test compression using SSN or equivalent compression approaches.
• Validate SSN topology, manage scan chain balancing and clock domain crossing issues.
• Integrate boundary-scan (IEEE 1149.x) and other test access mechanisms for chip-level testability.
• Generate and analyze ATPG patterns for stuck-at, transition, and path delay faults to achieve target coverage.
• Conduct DFT verification including Verilog/gate-level simulation and timing verification.
• Collaborate with physical design and cross-functional teams to resolve DFT/test timing challenges.
• Work with ATE engineers to prepare and validate timing and pattern files (STIL/WGL) for tester compatibility.
• Support silicon bring-up, production test debugging, diagnostics, and failure analysis.

Requirements

Must-have technical skills and experience for day-one contributions.

• Minimum ~3 years hands-on DFT design and verification experience (5+ years preferred).
• Strong understanding of scan-based test architectures, test compression, and hierarchical DFT implementation.
• Experience with DFT tools such as Siemens Tessent and ATPG generation tools.
• Experience in fault coverage analysis and gate-level DFT verification.
• Familiarity with ATE test flows and pattern validation on platforms like Advantest or Teradyne.
• Proficient scripting skills for DFT automation (TCL, Perl, or Python).
• Experience validating SSN topology, scan chain balancing, and clock-domain issues.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.