Senior DFT Engineer

Job Title

Senior DFT Engineer

Role Summary

Senior engineer responsible for defining and implementing design-for-test (DFT) architecture for SoC and block levels, supporting post-silicon bring-up, and collaborating with product, test, physical design and CAD teams. The role focuses on optimizing test cost, achieving high test coverage, and enabling reliable production test flows.

Experience Level

Senior — 4–8 years of industry experience in the DFT domain.

Responsibilities

Primary responsibilities cover DFT architecture, implementation, and post-silicon support across block and top-level activities.

• Define and optimize DFT architecture (scan partitioning, compression, at-speed, IR/low-power strategies, MBIST, JTAG boundary scan).
• Develop and maintain SCAN and MBIST insertion flows and ATPG flows for multiple fault models.
• Create timing constraints for SCAN/MBIST modes and resolve timing violations; run pattern simulations.
• Support post-silicon bring-up: work with evaluation/test teams on ATE, perform failure analysis, and support yield/test cost improvements.
• Collaborate closely with physical design and CAD tool teams throughout the development cycle.
• Improve DFT methodology to align with industry best practices and new technologies.
• Mentor and guide new team members on flows, methodology, and execution.

Requirements

Listing of must-have and preferred qualifications for successful candidates.

• Must-have: 4–8 years experience in DFT domain with hands-on post-silicon activities and experience bringing one or more products from architecture to production.
• Strong scripting skills (Perl, Python, Tcl) and good command of HDLs.
• Proven ability to work and communicate effectively with distributed product, test, and CAD teams.
• Willingness to travel (~10%).
• Nice-to-have: Experience with Tessent DFT tools (SCAN, MBIST, LBIST, OCC, EDT, SSN, Boundary Scan), familiarity with deep-submicron effects, low-power implementation using UPF/CPF, and experience with Cadence implementation tools (Genus, Tempus).
• Prior exposure to timing closure or physical design is an added plus.

Education Requirements

Not specified.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.