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Senior DFT Engineer

NVIDIA
August 19, 2026
Full-time
Remote friendly (Santa Clara, California, United States)
United States
$168,000 - $310,500 USD yearly
DFT Jobs, Level - Senior

Job Title

Senior DFT Engineer

Role Summary

Design-for-Test (DFT) engineer on the DFX Architecture team responsible for defining and deploying DFT architectures, verification, and post-silicon validation for complex ASICs. Work with cross-functional teams to implement test access mechanisms, BIST, scan compression, and production workflows for NVIDIA products.

Experience Level

Senior β€” typical experience expectations: BSEE with 8+ years, MSEE with 5+ years, or PhD with 3+ years in DFT or related domains.

Responsibilities

Main responsibilities include design, verification, and productization of DFT/DFX features and mentoring junior engineers.

  • Design and implement test access mechanisms, IO BIST, memory BIST, and scan compression for advanced chips.
  • Define, prototype, and deploy next-generation DFX architectures (high-speed test access, in-system-test, ISO26262 diagnostics, silicon debug and bring-up, productization, lifecycle management).
  • Collaborate with system architecture, chip architecture, ASIC design, verification, CAD, VLSI, software, and operations teams to productize test methodologies.
  • Deliver efficient workflows and tools to integrate DFT features into production flows for GPUs and related platforms.
  • Mentor and guide junior engineers on test design trade-offs, cost vs. quality, and debug strategies.

Requirements

Key technical skills and experience required. Degree details are listed under Education Requirements below.

  • Must-have: Demonstrated expertise in scan test planning, BIST for memories and IOs, fault modeling, ATPG, and fault simulation.
  • Must-have: Strong analytical skills for verification and validation of test patterns and logic on complex, multi-million-gate designs using vendor tools.
  • Must-have: Practical exposure to RTL & clock design, static timing analysis (STA), place-and-route, and power trade-offs.
  • Must-have: Experience with silicon debug and bring-up on ATE, including pattern formats, failure processing, and test program development.
  • Must-have: Strong written and verbal communication skills and ability to work across functions.
  • Nice-to-have: Programming/scripting experience in Perl, Python, or Tcl to automate flows and tools.

Education Requirements

Bachelor of Science in Electrical Engineering (BSEE) with 8+ years of relevant experience, Master of Science in Electrical Engineering (MSEE) with 5+ years, or PhD with 3+ years in DFT or related domains (electrical engineering, computer engineering, computer science, or equivalent). The posting allows equivalent practical experience in lieu of degree.


About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.

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Date Posted: 2026-08-19