Senior DFT Engineer

Job Title

Senior DFT Engineer

Role Summary

Lead the design-for-test (DFT) architecture and implementation for high-performance AI ASICs. Work with RTL/physical design, CAD methodology, STA, and post-silicon teams to ensure robust testability, timing closure in DFT mode, and successful silicon bring-up.

Experience Level

Senior-level. The role expects 5+ years of industry experience in DFT for high-performance SoC/ASIC designs.

Responsibilities

Primary responsibilities include architecting and delivering DFT structures and test flows, coordinating cross-functional sign-off, and supporting silicon bring-up and debug.

• Define and implement SCAN, MBIST, and JTAG debug structures and associated test plans.
• Drive creation of ATPG and MBIST test vectors and test pattern translation.
• Develop DFT timing constraints; coordinate with Physical Design and STA sign-off for timing closure in DFT mode.
• Support post-silicon bring-up: debug test patterns on silicon and resolve issues on ATE.
• Collaborate with CAD methodology to introduce optimizations and AI-driven improvements to DFT implementation.
• Perform yield estimation, test optimization, and work on scan compression and related yield learning activities.

Requirements

Must-have technical skills and relevant experience.

• 5+ years of hands-on DFT experience for large SoC/ASIC designs.
• Practical experience with SCAN, MBIST, ATPG tools and test generation processes.
• Domain expertise in ATPG, test pattern translation, scan compression, MBIST, LBIST, and IEEE 1500.
• Familiarity with ATPG Streaming SCAN Network (SSN) implementations.
• Experience with UDFMs such as Cell Aware and Small Delay Defect methodologies.
• Experience with silicon lab bring-up and debugging DFT test sequences on ATE.
• Strong RTL-to-GDS understanding and formal equivalence awareness.
• Proficient coding skills in Tcl and Python for DFT flows and automation.
• Effective interpersonal and organizational skills for cross-team collaboration.

Nice-to-have:

• Prior work on AI/ML accelerator chips or other high-performance ASICs.
• Experience introducing methodology or automation improvements within CAD teams.

Education Requirements

Bachelor's or M.S. in Computer Engineering, Electrical Engineering, or a related technical field — or equivalent practical industry experience.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.