Senior DFT Design Engineer
Intel CorporationJob Title
Senior DFT Design Engineer
Role Summary
Join the GPU Hardware IP (GHI) DFT team within Intel's Data Center Group to design and validate design-for-test (DFT) infrastructure for graphics and visual computing blocks. The role focuses on RTL/GLS validation, ATPG/scan, automation, timing analysis, and post-silicon debug to enable high-quality GPU IP for SoC integration.
Experience Level
Senior. Typical experience: equivalent of 4+ years with a Bachelor's (or reduced years with advanced degrees as listed in Education Requirements).
Responsibilities
Key responsibilities include design, validation, and support activities to ensure testability and integration quality for GPU IP blocks.
- Design and validate scan/ATPG features; perform RTL/GLS validation and timing analysis for DFT.
- Develop or contribute to trace/pattern generation and ATPG content; support post-silicon enabling and debug.
- Write RTL, simulate, and qualify logic for graphics IP (graphics, compute, display, media) for integration into SoCs.
- Participate in architecture and microarchitecture definition for assigned blocks.
- Optimize RTL for power, performance, area, timing, and physical implementation constraints.
- Define and review verification plans, drive unit-level verification, and resolve failing RTL tests.
- Collaborate with SoC integration teams to ensure correct integration and handoff of GPU blocks.
Requirements
Required technical skills and desirable additions are listed below.
- Must-have: Practical experience with scan, ATPG, or other DFT features.
- Must-have: SoC or IP DFT design, integration, or verification experience.
- Must-have: Experience with EDA tools such as Siemens Tessent (or other ATPG tools) and simulation/debug tools (e.g., Synopsys VCS).
- Nice-to-have: Silicon enabling, test pattern development, or post-silicon debug experience.
- Nice-to-have: Design automation skills and proficiency in programming or scripting languages for flow development.
- Nice-to-have: Familiarity with structural design flows (timing, routing, placement, clocking) and high-volume manufacturing test flows.
- Nice-to-have: Experience with 3D, media and display graphics pipelines and SoC architecture.
Education Requirements
Minimum: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related STEM field plus 4+ years industry experience; OR Master’s in EE/CE or related STEM plus 3+ years; OR PhD in EE/CE or related STEM plus 1+ years. Experience may be obtained through a combination of degree, research, prior jobs, or internships (equivalent practical experience is acceptable as described).
About the Company
Company: Intel Corporation
Headquarters: Santa Clara, California, USA
Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.
