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Senior DFT Design Engineer

Altera
October 13, 2026
Full-time
On-site
San Jose, California, United States
$187,000 - $270,700 USD yearly
DFT Jobs, Level - Senior

Job Title

Senior DFT Design Engineer

Role Summary

As a Senior DFT Design Engineer you will define and implement DFT architecture and flows for complex SoC and multi-die designs including FPGA, processors, DSP, SERDES, and IO. You will work with IP/integration and test teams to deliver manufacturable test solutions, ATPG, and pre-silicon validation.

Experience Level

Senior - typically 8+ years of relevant DFT experience (see Education Requirements for degree and equivalency guidance).

Responsibilities

Primary responsibilities include DFT architecture, implementation, validation, and collaboration to meet manufacturing test goals.

  • Define and implement DFT architectures and specifications for FPGA, processor, DSP, SERDES, IO, and multi-die designs.
  • Perform test logic insertion, ATPG pattern generation, and pre-silicon validation at RTL and gate level.
  • Create and maintain test mode timing constraints and support STA-related timing for test modes.
  • Collaborate with IP, integration, and test-development teams for silicon bring-up, debug, and production readiness.
  • Develop and improve DFT methodology, automation, and flows to increase scalability and efficiency.
  • Optimize test coverage, reduce test cost, and support yield improvement and debug efforts.

Requirements

Must-have technical skills and experience:

  • 8+ years of DFT design and verification at RTL and gate level (as stated in the job qualifications).
  • Experience with EDA tools: synthesis, scan insertion, ATPG, simulation/debug, and static timing analysis tools.
  • Design automation experience and proficiency in scripting (Perl, TCL, or similar).
  • Experience implementing test logic insertion and ATPG flows for complex digital and mixed-signal IP.
  • Practical experience collaborating with design and test teams for silicon bring-up and production diagnostics.

Nice-to-have:

  • Experience with test compression and BIST (MBIST/LBIST) and advanced fault models.
  • Prior work on 2.5D/3D multi-die packaging or high-speed IO/SerDes DFT.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (with 10+ years' industry experience) OR Master's degree in Electrical Engineering, Computer Engineering, or a related field (with 8+ years' industry experience). The posting indicates equivalent practical experience may satisfy degree requirements.


About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.

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Date Posted: 2026-10-13