Senior Design Verification Engineer - TeraWave

Job Title

Senior Design Verification Engineer - TeraWave

Role Summary

Senior verification engineer on the ASIC & Networking team responsible for defining and executing verification strategy, methodology, and infrastructure for TeraWave's in-house silicon program (IP through full SoC). Focus areas include verification planning, automation, regression/CI, and building AI-enabled verification capabilities.

Experience Level

Senior-level. Minimum five years' professional experience in ASIC or SoC functional verification is expected.

Responsibilities

Lead verification planning and execution, build verification infrastructure, and ensure sign-off readiness.

• Own verification planning and execution for complex blocks and subsystems, from test plan through sign-off.
• Translate design specifications into verification strategies, measurable coverage goals, and risk identification.
• Select verification methods (constrained-random, formal, directed) and apply appropriately.
• Develop verification environments, reference models, scoreboards, protocol monitors, coverage components, and assertions.
• Drive functional coverage closure, maintain regression health, and coordinate sign-off across simulation and formal results.
• Build regression and CI systems and define reuse strategy across IP, subsystem, and SoC levels.
• Apply and extend AI-assisted verification tooling for stimulus generation, regression triage, and coverage analytics.
• Review testbench architecture and debug methodology; mentor junior engineers in verification methodology.

Requirements

Core technical requirements for the role. Education details are listed separately under Education Requirements.

• Minimum five years' experience in ASIC or SoC functional verification.
• Hands-on expertise in SystemVerilog and UVM or formal testbench development and maintenance.
• Experience with metric-driven verification: planning, assertions, and functional coverage closure.
• Experience verifying complex digital control and datapath logic, including RTL and system-level debug.
• Familiarity with constrained-random simulation, formal methods, and processor-driven SoC testing.

Nice-to-have:

• Background in wireless communications, modem/baseband, DSP, or space-based communications.
• Experience with LDPC, FEC, framing, beamforming logic, interconnect/NoC verification, ECC/reliability, or fault injection.
• Formal verification experience on production silicon and experience verifying connectivity, register maps, arbitration, CDC, or security properties.
• Experience developing C-based or portable stimulus for SoC, CPU boot, and firmware-driven test scenarios.
• Experience applying AI/ML/LLM tooling to stimulus generation, regression triage, or coverage analysis.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field, or equivalent practical experience.

About the Company

Company: Blue Origin

Headquarters: Kent, Washington, United States

Blue Origin is an American aerospace company developing technologies for spaceflight, including reusable launch vehicles, orbital and suborbital systems, and space infrastructure for commercial and government customers.