Senior Design Verification Engineer – High Performance CPU Core

Job Title

Senior Design Verification Engineer – High Performance CPU Core

Role Summary

Senior engineer responsible for functional verification of high-performance out-of-order CPU core units. The role works on block- and core-level verification across areas such as Frontend, Midcore, Load-Store Unit, and hardware prefetch.

Collaborate with architecture, RTL, performance, and verification teams to identify risks, drive debug and fixes, and deliver signoff-quality verification results.

Experience Level

Senior. The posting specifies a minimum of 3+ years of relevant verification experience.

Responsibilities

Primary responsibilities include planning, implementing, and executing verification for high-performance CPU core features and integrations.

• Own verification planning and execution for assigned CPU core areas from block to core integration.
• Create verification strategies and test plans based on CPU architecture and microarchitectural behavior.
• Develop and maintain verification environments, testbenches, assertions, checkers, scoreboards, stimulus, and coverage models.
• Design and run directed and constrained-random tests targeting corner cases in branch prediction, instruction fetch, pipeline interactions, issue/dispatch, hazards, load/store ordering, memory consistency, and prefetch behavior.
• Analyze failures, isolate root cause, and drive fixes across RTL, testbench, and test content.
• Write and analyze functional coverage; close coverage gaps to achieve verification completeness and signoff.
• Contribute reusable DV methodology, automation, and infrastructure to improve team productivity.
• Collaborate with architecture and design teams to clarify specifications and improve debugability.

Requirements

Must-have technical skills and experience required for independent ownership of CPU verification tasks.

• 3+ years of experience in IP, CPU/core, or SoC functional verification (degree requirements are listed under Education Requirements).
• Strong hands-on experience with SystemVerilog and UVM-based verification methodologies.
• Solid understanding of computer architecture and CPU microarchitecture fundamentals.
• Experience in test planning, testbench development, constrained-random verification, failure analysis, coverage analysis, and coverage closure.
• Strong debug skills and ability to translate architectural intent into verification strategy and execution.
• Proficient programming and scripting skills for building scalable verification solutions.

Nice-to-have:

• Direct experience with high-performance out-of-order core verification.
• Experience in Frontend, Midcore, Load-Store Unit, memory ordering/consistency, or hardware prefetch verification.
• Familiarity with formal verification, emulation, or performance-oriented verification flows.
• Experience building reusable infrastructure and improving team-wide verification methodology.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field is required (as stated in the posting). Equivalent practical experience is not explicitly listed.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.