Senior Design Verification Engineer - FPGA

Job Title

Senior Design Verification Engineer - FPGA

Role Summary

Join an engineering team developing FPGA-based signal processing and control functions for electronic warfare systems. The role focuses on creating and executing verification environments and reusable verification IP to assure FPGA designs meet requirements.

This position is full-time, on site, and works with engineers across multiple U.S. locations to drive verification processes and methodology improvements.

Experience Level

Senior-level. The posting indicates 4–6 years of relevant work experience or equivalent experience; the role expects demonstrated independent execution and leadership on verification tasks.

Responsibilities

Primary duties include developing and executing verification activities for FPGA designs.

• Develop configurable, self-checking testbenches in SystemVerilog/UVM and/or VHDL.
• Create constrained-random, metric-driven test plans and verification strategies for FPGA signal-processing and control functions.
• Collect, analyze, and act on coverage and other verification metrics to improve test effectiveness.
• Create reusable Verification IP for cross-project use.
• Implement and execute test plans, drive tasks to closure, and support multiple projects concurrently.
• Work with cross-site engineering teams and subject-matter experts to resolve design and verification issues.
• Contribute to evolution of verification processes and mentor junior engineers as needed.

Requirements

Must-have technical skills, security eligibility, and workplace expectations.

• Experience developing constrained-random, self-checking testbenches in SystemVerilog/UVM, OVM, and/or VHDL.
• Experience with FPGA/ASIC design and verification tools (examples: Mentor Questa or Cadence).
• Proven ability to execute to schedule, multitask across projects, and drive tasks to closure.
• Strong written and verbal communication and documentation skills.
• Ability to work effectively in a multi-site U.S. environment.
• Must be able to obtain a U.S. Secret security clearance; U.S. person/citizenship is required.
• Travel up to 10%.

Preferred (nice-to-have):

• Perl or Python scripting.
• C++ or Java experience.
• Familiarity with Git, Jira, BitBucket.
• Digital signal processing and MATLAB/Simulink.
• Working knowledge of VHDL and FPGA design experience.
• Experience creating reusable Verification IP and leading small teams.
• Experience driving process improvements and mentoring engineers.

Education Requirements

Bachelor's degree required or equivalent practical experience; the posting specifies 4–6 years of related work experience as an alternative to additional academic credentials.

About the Company

Company: BAE Systems

Headquarters: London, United Kingdom

Global defense, aerospace and security company delivering products and services for air, land and naval forces, advanced electronics, cyber and intelligence solutions, and space and mission systems for government and commercial customers.