Senior Design Verification Engineer – CPU Core Verification (Vector)

Job Title

Senior Design Verification Engineer – CPU Core Verification (Vector)

Role Summary

Senior engineer responsible for planning and executing functional verification for high-performance out-of-order CPU cores, with significant scope in RISC-V Vector Extension (RVV) and vector microarchitecture verification.

Work within the CPU Design Verification organization to define verification strategies, build reusable infrastructure, and collaborate with architecture, RTL, performance, and verification teams to reach signoff quality.

Experience Level

Senior-level. 5+ years of relevant experience in IP, CPU/core, or SoC functional verification.

Responsibilities

Deliver verification from block-level through core integration and close coverage gaps to achieve signoff quality.

• Own verification planning and execution for assigned CPU core areas, including Frontend, Midcore, Load-Store Unit, Hardware Prefetch, and Vector Unit.
• Create verification strategies and test plans derived from CPU architecture and microarchitectural behavior.
• Develop and maintain verification environments, assertions, checkers, scoreboards, stimulus, and coverage models.
• Define and run directed and constrained-random tests targeting corner cases in branch prediction, fetch, pipeline interactions, issue/dispatch, hazards, memory ordering, and prefetch behavior.
• Drive verification of RVV and vector-unit correctness: vector arithmetic, memory ops, masking, configuration-dependent execution, exception behavior, and scalar-vector interactions.
• Analyze failures, isolate root cause, and coordinate fixes across RTL, test infrastructure, and test content.
• Write and analyze functional coverage; close coverage gaps to ensure verification completeness.
• Contribute reusable DV methodology, automation, and infrastructure to improve team productivity across CPU generations.

Requirements

Concise list of must-have skills and desirable additions.

Must-have:

• 5+ years of experience in IP, CPU/core, or SoC functional verification.
• Strong hands-on experience with SystemVerilog-based verification and modern verification methodologies.
• Solid understanding of computer architecture and CPU microarchitecture fundamentals.
• Experience with test planning, verification environment development, stimulus generation, failure analysis, and coverage closure.
• Strong debug skills and ability to translate architectural intent into verification strategy and execution.
• Programming and scripting skills for building scalable verification solutions.
• Experience in one or more CPU areas: Frontend, Midcore, Load-Store Unit, memory ordering/consistency, Hardware Prefetch, or Vector Unit verification.

Nice-to-have:

• Direct experience with high-performance out-of-order CPU core verification.
• Experience with RISC-V Vector Extension (RVV), SIMD, or vector-processor verification and vector memory behaviors.
• Experience developing assertions, checkers, and scoreboards for control-heavy or ordering-sensitive CPU behavior.
• Familiarity with formal verification, emulation, or acceleration for difficult verification problems.
• Experience collaborating with performance, compiler, system verification, and software teams.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.