Senior Design Verification Engineer – Cache Verification

Job Title

Senior Design Verification Engineer – Cache Verification

Role Summary

Senior individual-contributor responsible for planning and executing functional verification of cache and memory subsystems, emphasizing coherency, ordering, correctness, and subsystem integration. Partners with architecture, design, and verification teams to deliver signoff-quality verification and improve team methodology.

Experience Level

Senior — typically 3+ years of relevant verification experience; individual-contributor role.

Responsibilities

Primary responsibilities include designing verification strategies, building robust environments, and driving closure of verification tasks for cache and memory subsystems.

• Develop verification strategies and test plans for cache and memory-subsystem features.
• Implement and maintain SystemVerilog/UVM environments, checkers, scoreboards, assertions, stimulus, and coverage models.
• Create directed and constrained-random tests targeting coherency, ordering, concurrency, backpressure, and integration corner cases.
• Analyze failures, isolate root causes, and drive fixes across RTL, testbench infrastructure, assertions, and test content.
• Write and analyze functional coverage and close coverage holes to achieve verification signoff.
• Collaborate with architecture, design, and verification teams to clarify requirements and improve verification early in the cycle.
• Contribute reusable methodology, automation, and debug tooling to raise team productivity and verification quality.

Requirements

Must-have technical skills and experience. Education listed separately below.

• 3+ years of IP, subsystem, or SoC functional verification experience, preferably in CPU, memory-system, or cache verification.
• Hands-on experience with SystemVerilog and UVM-based verification.
• Solid understanding of computer architecture and memory-system behavior, including cache coherency and ordering concepts.
• Experience creating test plans, building testbenches, writing assertions, analyzing coverage, and debugging complex design issues.
• Strong problem-solving skills and the ability to work effectively across design and verification teams.

Preferred / nice-to-have:

• Direct experience verifying cache or memory-subsystem functionality in multicore systems.
• Experience with subsystem integration and multi-interface protocol interactions.
• Familiarity with Python or similar scripting for automation; experience with formal verification, performance-oriented verification, or emulation/FPGA-assisted debug is a plus.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.