Senior Design Verification Engineer – Cache Verification

Job Title

Senior Design Verification Engineer – Cache Verification

Role Summary

Senior individual-contributor verification engineer responsible for validating cache and memory-subsystem functionality with emphasis on coherency, ordering, correctness, and subsystem integration. Member of the horizontal cache verification team who designs verification strategies, builds test environments, and drives closure of complex issues in RTL and testbench infrastructure.

Work contributes to the quality and correctness of RISC-V compute platforms used in performance-sensitive applications.

Experience Level

Senior — the role expects experienced engineers; the posting requests approximately 3+ years of relevant verification experience.

Responsibilities

Key responsibilities include:

• Develop verification strategies and test plans for cache and memory-subsystem areas.
• Design, implement, and maintain verification environments, checkers, scoreboards, assertions, stimulus, and coverage models targeting coherency, ordering, flow control, and error scenarios.
• Create and run directed and constrained-random tests to expose corner cases in coherency, concurrency, backpressure, and integration.
• Analyze failures, isolate root cause, and drive fixes across RTL, testbench infrastructure, assertions, and test content.
• Collaborate with architecture, design, and verification teams to clarify requirements and improve verification quality early in the cycle.
• Write and analyze functional coverage and close coverage holes to meet verification signoff criteria.
• Contribute reusable methodology, automation, and debug improvements to raise team productivity and verification quality.

Requirements

Must-have skills and experience:

• 3+ years of IP, subsystem, or SoC functional verification experience, preferably involving CPU, memory-system, or cache verification.
• Strong hands-on experience with SystemVerilog and UVM-based verification.
• Solid understanding of computer architecture and memory-system behavior, including cache coherency and ordering concepts.
• Experience creating test plans, building testbenches, writing assertions, analyzing coverage, and debugging complex design issues.
• Strong problem-solving skills and ability to work effectively across design and verification teams.

Nice-to-have:

• Direct experience verifying cache or memory-subsystem functionality in multicore systems.
• Experience with subsystem integration and multi-interface protocol interactions.
• Familiarity with scripting and automation using Python or similar languages.
• Experience with formal verification, performance-oriented verification, or emulation/FPGA-assisted debug.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.