Senior Design Verification Engineer

Job Title

Senior Design Verification Engineer

Role Summary

Responsible for block- and subsystem-level design verification of advanced out-of-order CPU cores. Work closely with micro-architects and RTL designers to verify execution pipelines, memory systems, and coherence protocols using coverage-driven methodologies.

Primary responsibilities include verification planning, SystemVerilog/UVM testbench development, coverage closure, and debugging through silicon correlation.

Experience Level

Senior — typically 5–10 years of ASIC/SoC/IP design verification experience.

Responsibilities

Key responsibilities include:

• Own verification planning and execution for CPU blocks and subsystems.
• Drive verification for front-end, rename/ROB/issue/execute paths, retirement and exceptions, and load-store unit behavior.
• Verify caches, TLBs, MMU and coherence interfaces and memory-ordering compliance.
• Develop and maintain SystemVerilog/UVM testbenches, agents, monitors, scoreboards, and reference models.
• Implement constrained-random stimulus, directed tests, and self-checking mechanisms for architectural state and memory ordering.
• Define and track functional, code, and assertion coverage; write and maintain SVA assertions for key micro-architectural properties.
• Analyze regressions, triage failures, debug complex corner cases, and drive issues to closure with design and architecture teams.
• Collaborate with micro-architecture, RTL, performance/modeling, and post-silicon teams; mentor junior engineers and contribute to DV methodology improvements.

Requirements

Must-have:

• 5–10 years of ASIC/SoC/IP design verification experience focused on CPU or high-performance pipelines.
• Direct experience verifying out-of-order or superscalar CPU cores or similar high-performance pipelines.
• Strong proficiency in SystemVerilog and UVM (or equivalent class-based DV methodology).
• Solid understanding of CPU micro-architecture: fetch/decode, rename, ROB, issue/execute, bypassing, commit; LSU, store buffer, atomics, fences; L1 caches and TLBs.
• Hands-on experience with constrained-random and coverage-driven verification, SVA assertion development, and industry simulators (e.g., VCS, Xcelium, Questa) and debug tools (e.g., Verdi/DVE).
• Strong problem-solving and debug skills for complex corner-case bugs; effective communication and teamwork; ability to work independently on complex blocks.
• Must be authorized to work in India and able to satisfy export-control and background-check requirements.

Nice-to-have:

• Experience with post-silicon validation and correlating pre/post-silicon issues.
• Background collaborating with performance or modeling teams.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.