Senior Design Verification Engineer

Job Title

Senior Design Verification Engineer

Role Summary

Design Verification Engineer on the Silicon Chassis team responsible for owning verification of interconnect and chassis IP blocks from planning through coverage closure. Works with architecture, design, and software teams to deliver verification environments, drive coverage closure, and ensure quality and schedule on assigned blocks.

Requires on-site presence in Bangalore.

Experience Level

Senior-level — requires 5+ years of relevant design verification experience (IP-level and subsystem exposure).

Responsibilities

Primary responsibilities include planning, executing, and owning verification for assigned IP and subsystem features.

• Own verification planning and execution; drive test plans to coverage closure and quality signoff.
• Design and build scalable, reusable verification environments (testbenches, checkers, constrained-random tests, debug infrastructure).
• Analyze simulation failures, perform root-cause analysis, and drive fixes to closure; own end-to-end debug for assigned blocks.
• Develop and drive functional coverage models and coverage closure activities.
• Collaborate with architecture, design, and software teams on spec reviews and bug triage.
• Improve verification automation, regression quality, and development efficiency.
• Mentor junior engineers on verification practices, debugging, and code quality.

Requirements

Must-have technical skills and experience:

• Proven IP-level design verification experience and exposure to subsystem-level verification.
• Strong proficiency in SystemVerilog and UVM methodology.
• Hands-on experience verifying RAS features: error injection, fault propagation, error logging, recovery sequences.
• Working knowledge of interconnects and bus protocols such as AMBA AXI/ACE/CHI, PCIe, CXL, or UCIe; understanding of cache coherency and memory consistency models.
• Experience writing SystemVerilog Assertions (SVA) for protocol checking.
• Experience building coverage models and driving test plans to closure.
• Strong debugging skills with ability to trace transactions across multiple protocol domains.
• Solid coding skills for verification infrastructure and testbench development.

Nice-to-have:

• Telemetry/performance counter verification or debug/trace infrastructure experience.
• Familiarity with AI-assisted verification workflows (LLM-assisted code review or generation).
• Prior work on Intel fabric or SoC interconnect IPs.

Education Requirements

BS or MS in Electrical Engineering, Computer Science, or a related field (as stated in minimum qualifications).

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.