Senior Design Verification Engineer

Job Title

Senior Design Verification Engineer

Role Summary

Senior Design Verification Engineer responsible for planning and executing RTL-to-gate verification for ASIC subsystems. Works on scalable SystemVerilog/UVM testbenches, constrained-random and directed tests, coverage closure, gate-level validation and automation of regression flows. Role interfaces with architects, RTL designers, and system teams and may use emulation for system-level verification.

Experience Level

Senior-level engineer. Requires substantial hands-on verification experience with SystemVerilog/UVM and industry simulators; specific years of experience not specified.

Responsibilities

Deliver verification solutions across module to system level, drive coverage closure and automate regression and debug.

• Design and implement scalable UVM/SystemVerilog testbenches and verification environments.
• Develop verification plans from architecture and specifications.
• Write, run, and debug constrained-random and directed tests; close functional and code coverage.
• Run and analyze gate-level simulations for power-up and timing validation.
• Automate regressions, test generation, and failure triage with scripting.
• Use emulation platforms and C-based tests for processor-in-loop or system-level verification as needed.
• Collaborate with RTL designers, architects, and system teams to validate memory, MMU, DSP and bus interactions.

Requirements

Must-have technical skills and tools for day-to-day verification work; preferred items listed separately.

• Languages & scripting: Strong proficiency in SystemVerilog and scripting (Python, Perl, or Tcl).
• Methodology: Hands-on experience with UVM (Universal Verification Methodology).
• Verification concepts: Constrained-random verification, assertions (SVA), functional and code coverage closure.
• Simulators & tools: Experience with industry simulators (Cadence Xcelium preferred; Synopsys VCS or Siemens Questa acceptable).
• Gate-level & power: Experience running gate-level simulations and knowledge of power-aware verification flows.
• Protocols: Familiarity with common protocols such as AMBA (AXI/AHB/APB).
• Automation: Develop scripts to automate regression runs and triage failures.
• Preferred / Nice-to-have: Formal verification experience; power-aware verification (UPF/CPF); emulation (Cadence Palladium or similar); MMU, SRAM/memory-subsystem, DSP verification; modeling (RNM/behavioral models).

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field (specified in the source).

About the Company

Company: eInfochips

Headquarters: Bengaluru, India

eInfochips is a product engineering and semiconductor design services company offering embedded software, SoC design and verification, testing, and IoT solutions. It operates as part of Arrow Electronics, serving clients across industries worldwide.