Senior Design Verification Engineer

Job Title

Senior Design Verification Engineer

Role Summary

Independently own design verification for interconnect and chassis IP blocks from planning through coverage closure. Build scalable, reusable verification environments and drive quality and schedule for assigned IP and subsystem features.

Work closely with architecture, RTL design, and software teams; contribute across disciplines and mentor junior engineers as needed.

Experience Level

Senior-level. The posting specifies approximately 8–12 years of relevant design verification experience.

Responsibilities

Deliver verification plans, environments, and closure for assigned IP and subsystem blocks; be accountable for quality and schedule.

• Own verification planning and execution for assigned IP blocks and features through coverage closure.
• Design and deliver scalable testbenches, checkers, constrained-random tests, and debug infrastructure.
• Analyze failures, perform root-cause analysis, and drive fixes to closure; own end-to-end debug for assigned blocks.
• Drive functional coverage planning and contribute to quality signoff.
• Contribute to both simulation and formal verification efforts and improve automation and regression quality.
• Collaborate with architecture, design, and software teams on specs, bug triage, and feature clarification.
• Mentor junior engineers on verification practices and debugging techniques.

Requirements

Must-have:

• Proven IP-level design verification experience and exposure to subsystem-level verification.
• Expertise with interconnects and bus protocols such as AMBA AXI/ACE/CHI, PCIe, CXL, or UCIe; working understanding of cache coherency and memory consistency models.
• Strong background in simulation-based methodologies (UVM, SVA, ABV) and coverage-driven verification.
• Hands-on coding proficiency in SystemVerilog/UVM, C/C++, and Python; deliver clean, reusable verification code and automation.
• Comfort using AI-assisted development tools as part of coding, debugging, and test development workflows.
• Effective collaboration and communication skills across architecture, design, and software teams.

Nice-to-have:

• Experience with formal verification tools (JasperGold, VC Formal) and emulation or FPGA-based verification.
• Exposure to verification of debug, trace, clock/power management, RAS, or security features.
• Familiarity with RTL concepts, physical design, or CAD tool flows; prior work with system IPs (MMU/IOMMU, interrupt controllers).

Education Requirements

BS or MS in Electrical Engineering, Computer Science, or a related technical field is specified in the posting (listed with 8–12 years of relevant design verification experience).

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.