Senior Design Engineer (Physical IP)

Job Title

Senior Design Engineer (Physical IP)

Role Summary

Member of the Solutions Engineering Physical IP team responsible for layout development of custom standard cells in advanced sub-3nm process nodes. The role delivers high-performance, area-optimized, DRC-clean logic libraries used in SoCs and custom digital IP across infrastructure, client, automotive, and IoT segments.

The engineer will work closely with circuit designers, QA and automation teams to produce and validate physical layouts and signoff packages for next-generation nodes.

Experience Level

Senior. The posting specifies 3+ years of custom layout experience in logic standard cell development.

Responsibilities

Deliver and validate standard-cell physical layouts and support library integration and signoff.

• Design compact, PPA-optimized standard cells (inverters, muxes, flops, complex gates).
• Collaborate with circuit designers to translate schematics into layout and meet timing/area targets.
• Drive DRC and LVS closure and perform layout debugging and root-cause analysis for signoff issues.
• Handle cell abutment, profiling, pin accessibility, and integration constraints for logic libraries.
• Address layout-dependent effects, multi-patterning/EUV compliance and advanced-node constraints.
• Support library validation flows and QA, including LEF/GDS/abstract view reviews for digital integration.
• Automate layout QA, regression checks, and PDK-driven verifications via scripting.
• Participate in library quality audits, create signoff packages, and maintain delivery documentation.

Requirements

Must-have technical skills and relevant experience.

• 3+ years of custom layout experience in logic standard cell development.
• Experience at advanced nodes (5nm, 3nm, or 2nm) with FinFET/GAA technologies.
• Proficiency with Cadence Virtuoso and standard cell layout flows.
• Deep understanding of advanced DRC rules, LVS methodologies, multi-patterning constraints, and signoff practices.
• Strong skills in cell layout optimization for power, performance, and area, and knowledge of pin accessibility and physical synthesis considerations.
• Scripting/automation experience (Python, PERL, SKILL, TCL) to automate layout tasks and QA flows.
• Familiarity with version control, configuration management, and flow automation; strong documentation and cross-team communication skills.
• Ability to use AI tools and automation to improve productivity and solution quality.
• Nice to have: exposure to physical design implementation flow.

Education Requirements

Not specified.

About the Company

Company: Arm

Headquarters: Cambridge, United Kingdom

ARM is a global leader in semiconductor and software design, driving innovation in computing technology. The company specializes in designing processors and systems that provide the essential building blocks for electronic devices. ARM's architecture is widely used in smartphones, servers, and IoT devices, and its collaborative culture fosters bold thinking, diversity, and high-impact benefits for its talented workforce.