Senior Design Engineer — Custom Digital Hard Macros (Physical IP)

Job Title

Senior Design Engineer — Custom Digital Hard Macros (Physical IP)

Role Summary

Join the Physical IP team focused on custom and semi‑custom digital hard macros used across Arm CPU, GPU, NPU and SoC products. The role covers the full macro development lifecycle including RTL, implementation, timing, simulation, characterization and integration.

This is a hands‑on implementation role that collaborates with AMS, verification, DFT and SoC integration teams and participates in silicon bring‑up and correlation activities.

Experience Level

Senior; the posting specifies 2–5 years of relevant experience.

Responsibilities

Primary responsibilities include implementing and delivering digital hard macros and supporting their integration and validation.

• Design and implement custom and semi‑custom digital hard macros.
• Develop and maintain RTL, timing constraints (SDC), implementation scripts and automation flows.
• Execute synthesis, floorplanning, place‑and‑route, static timing analysis, physical verification and sign‑off flows.
• Analyze and debug timing, power, congestion, DRC/LVS and other implementation issues.
• Support functional, gate‑level and mixed‑signal simulation and characterization activities.
• Generate and validate deliverables: Liberty timing models, LEF abstracts, physical views and integration collateral.
• Review schematics and layout to understand macro operation and implementation tradeoffs.
• Collaborate with AMS, DFT, verification and SoC integration teams and participate in silicon validation and post‑silicon correlation.
• Contribute to methodology, scripting and automation improvements.

Requirements

Must‑have technical skills and experience to perform the role.

• Hands‑on experience with synthesis, floorplanning, place‑and‑route, static timing analysis and physical verification.
• Good understanding of RTL design and digital design fundamentals; experience with Verilog/SystemVerilog.
• Familiarity with implementation tools (examples: Cadence Innovus, Tempus, Genus or equivalents).
• Knowledge of timing constraints (SDC), CDC concepts and multi‑clock designs.
• Working knowledge of transistor‑level concepts, digital circuit operation and custom layout fundamentals.
• Familiarity with simulation methodologies (RTL, gate‑level, behavioral) and Liberty timing models.
• Experience with scripting languages such as Tcl or Python for automation.
• Strong analytical, debugging, problem‑solving, communication and teamwork skills.

Nice‑to‑have / preferred:

• Exposure to hard‑macro, memory, standard‑cell, custom digital or mixed‑signal IP development.
• Experience at advanced process nodes and familiarity with low‑power design methodologies.
• Exposure to metastability, asynchronous interfaces, reliability concepts and silicon validation/post‑silicon debug.

Education Requirements

Not specified.

About the Company

Company: Arm

Headquarters: Cambridge, United Kingdom

ARM is a global leader in semiconductor and software design, driving innovation in computing technology. The company specializes in designing processors and systems that provide the essential building blocks for electronic devices. ARM's architecture is widely used in smartphones, servers, and IoT devices, and its collaborative culture fosters bold thinking, diversity, and high-impact benefits for its talented workforce.