Senior Density Fill Development Engineer

Job Title

Senior Density Fill Development Engineer

Role Summary

Join Intel's Design Technology Platform (DTP) team to develop and deploy density-fill and physical verification software components used in Process Design Kits (PDKs). The role focuses on algorithm development, rule-deck implementation, automation, and validation to ensure manufacturability for advanced process nodes.

Experience Level

Senior level. Typical experience expectation per posted qualifications: Bachelor's + 8+ years, Master’s + 5+ years, or PhD + 2+ years in relevant fields; significant industry experience in physical verification, methodology development, or density/fill implementation.

Responsibilities

Deliver and maintain density-fill and physical verification toolchains and methodologies to ensure manufacturability compliance.

• Design, develop, and debug fill components within PDKs.
• Create algorithmic solutions using tools such as Calibre, ICV, and Pegasus to resolve density deficiencies and meet manufacturing rules.
• Develop, maintain, and debug physical verification rule decks and deploy them into production flows.
• Automate workflows and toolchains to improve efficiency, repeatability, and deployment across design teams.
• Develop test cases and validation systems to verify tool behavior and integration with design methodologies.
• Collaborate with process developers, design-rule owners, cross-functional teams, and external EDA vendors to define requirements and implement solutions.
• Document tools and workflows; produce training materials and user guides for customers and internal teams.

Requirements

Key technical must-haves and preferred skills for successful candidates.

• Must-have: 5+ years hands-on experience with an industry physical verification platform (Calibre, ICV, or Pegasus), including methodology development, rule-deck debugging, or production deployment.
• Must-have: 3+ years developing, maintaining, or debugging physical verification rule decks using SVRF, TVF, PXL, or PVL/PVTCL for DRC, density, or fill verification.
• Must-have: Strong understanding of semiconductor device physics, process technology, and design rules.
• Must-have: Experience developing algorithmic solutions for physical design challenges at advanced manufacturing nodes.
• Must-have: Proficiency with Unix/Linux environments and scripting/automation for tool deployment and workflows.
• Nice-to-have: Experience developing or owning density fill methodologies for nodes at 16nm and below.
• Nice-to-have: Familiarity with advanced physical verification techniques (DRC, density/fill modules) and custom layout tools (Cadence Virtuoso, Synopsys Custom Designer).
• Nice-to-have: Experience at foundries, OSATs, IDMs, or EDA vendors and proven cross-functional collaboration or leadership.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 8+ years of experience; or Master’s degree with 5+ years; or PhD with 2+ years. Fields referenced: Electrical Engineering, Computer Engineering, or related technical disciplines.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.