Senior Custom Memory Layout Design Engineer

Job Title

Senior Custom Memory Layout Design Engineer

Role Summary

Join Microsoft's Semi & Custom IP team within Silicon, Cloud Hardware, and Infrastructure Engineering to lead physical implementation and delivery of custom SRAM, register file (RF), and cache memory IP for AI accelerators and cloud silicon. The role focuses on physical implementation, verification, integration, and production readiness across advanced technology nodes.

Hybrid role with an expected on-site cadence of approximately 3 days per week (Raleigh, NC listed). Travel under 25%.

Experience Level

Senior — the position expects substantial relevant engineering experience and leadership on complex custom memory layout and signoff projects.

Responsibilities

Primary responsibilities include physical design, verification, integration, automation, and cross-team collaboration to deliver production-ready memory IP.

• Perform floorplanning, hierarchy development, placement, routing, and physical integration of custom SRAM, RF, cache and memory macro layouts.
• Collaborate with circuit designers, architects, physical design, CAD, foundry and SoC teams to optimize power, performance, area, reliability, and manufacturability.
• Execute physical verification and signoff activities: DRC, LVS, ERC, antenna, density, EMIR, reliability analysis, debug and closure.
• Produce production deliverables: GDS/OASIS, LEF abstracts, integration views, documentation and signoff packages for SoC integration.
• Develop and maintain layout methodologies, design-rule adoption, automation flows and scripting to improve productivity and quality.
• Identify technical risks, communicate status and tradeoffs, and support multiple memory programs across advanced nodes to meet program milestones.

Requirements

Must-have technical skills and compliance requirements followed by desired skills.

• Proven record delivering custom memory layouts and supporting their integration into SoCs (placement, routing, abstraction, signoff).
• Practical experience with physical verification and signoff flows (DRC, LVS, ERC, antenna, density, EMIR) and debugging closure issues.
• Strong automation and scripting skills (Python, SKILL, TCL, Perl or similar) to create layout productivity tools and flows.
• Ability to work cross-functionally with internal teams, external layout providers and foundries to meet program milestones.
• Ability to pass Microsoft Cloud Background Check and meet export-control eligibility requirements (citizenship or valid residency documentation as required).

Nice-to-have:

• Experience with Cadence Virtuoso and Siemens/Mentor Calibre physical verification tools.
• Experience with EMIR and reliability signoff tools (Ansys Totem, Cadence Voltus or equivalent).
• Experience with advanced nodes (5nm, 3nm or below), FinFET or Gate-All-Around technologies, and analog/mixed-signal layout considerations.
• Experience generating LEF/abstracts, integration views, timing collateral and delivering memory IP from specification through tapeout.
• Experience working with geographically distributed teams, contractors, vendors or design-service partners.

Education Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field + 1 year technical engineering experience; OR Master’s in EE/CE/CS or related + 4 years technical engineering experience; OR Bachelor’s in EE/CE/CS or related + 5 years technical engineering experience; OR equivalent practical experience is accepted.

About the Company

Company: Microsoft

Headquarters: Redmond, Washington, United States

Microsoft is a global technology company that develops and sells software, services, devices, and solutions. Known for its Windows operating system, Office suite, and Azure cloud platform, Microsoft aims to empower individuals and organizations around the world to achieve more. The company fosters a culture of innovation and inclusion, focusing on delivering trusted experiences to customers and partners globally.