Senior CPU Physical Design Engineer

Job Title

Senior CPU Physical Design Engineer

Role Summary

Deliver physical implementation and optimization of high-performance CPU designs from RTL to manufacturing within Intel's CPU Design team (Silicon and Platform Engineering Group).

Collaborate with architecture, logic, circuit, CAD and validation teams to meet goals for performance, power, area, and manufacturability. This role requires on-site presence in Austin, TX.

Experience Level

Senior level. Experience guidance: typical candidates have 6+ years with a Bachelor's, 4+ years with a Master's, or 2+ years with a PhD (per position minimum qualifications).

Responsibilities

Core responsibilities include physical implementation, verification, optimization, and flow/tool improvement.

• Perform full physical design flow: floorplanning, synthesis, place-and-route, clock-tree synthesis, and static timing analysis.
• Implement power/clock distribution and conduct noise, reliability, and layout verification checks for CPU blocks.
• Lead verification and signoff activities: formal equivalence, reliability verification, layout vs. schematic, and structural checks.
• Collaborate with logic, circuit, architecture, and EDA teams to optimize microarchitecture for power, area, and frequency.
• Develop and refine physical design methodologies and automation to improve flow efficiency and tapeout readiness.
• Work with EDA vendors to improve tools and enable high-speed, low-power CPU implementations.
• Analyze design results and recommend optimizations for current and future microarchitectures.

Requirements

Must-have technical skills and experience. Education degree requirements are summarized separately under Education Requirements below.

• Hands-on experience with physical design EDA tools (e.g., Synopsys Fusion Compiler, Cadence Genus/Innovus, or equivalent).
• Proficiency with scripting for tool automation and exploration (TCL, Perl, Python, or similar).
• Experience with backend design workflows: constraints management, CTS, STA, and layout verification.
• At least one tape-out on advanced process nodes and experience with RTL-to-GDS automation.
• Familiarity with AI/ML-based automatic place-and-route approaches for design efficiency and quality.
• Strong technical problem solving, ownership, communication, and cross-functional collaboration skills.

Nice-to-have:

• Low-power design techniques, multi-power-domain methodologies (MPP/UPF), and power analysis.
• Digital design fundamentals, CMOS process knowledge, and CPU microarchitecture experience.
• Experience collaborating with multiple EDA vendors and applying thermal/power reduction techniques.
• Power/performance optimization experience in APR flows.

Education Requirements

Minimum qualification paths stated: Bachelor's degree in Electrical or Computer Engineering (or related field) with 6+ years relevant experience; OR Master's in same field with 4+ years; OR PhD in same field with 2+ years. No specific certifications listed. (Education/degree requirements extracted from the posting.)

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.