Senior CPU Design Verification Engineer

Job Title

Senior CPU Design Verification Engineer

Role Summary

Own block- and subsystem-level design verification for advanced out-of-order (OoO) CPU cores. Work closely with micro-architects and RTL designers to verify front-end, pipeline, memory system, and coherence behaviors using coverage-driven methodologies.

Experience Level

Senior-level. Typically 5–10 years of ASIC/SoC/IP design verification experience, with direct experience verifying out-of-order or superscalar CPU cores or similar high-performance pipelines.

Responsibilities

Primary responsibilities focus on planning, developing, and executing verification for complex CPU blocks and subsystems, building testbenches, and driving closure of functional and coverage gaps.

• Drive verification for key OoO CPU blocks (front-end: fetch, branch prediction, decode; rename/register mapping; issue queues/schedulers; execution units; ROB, retirement, exceptions; LSU, store buffer, atomics/LR-SC; L1 caches, TLBs, MMU and coherence interfaces).
• Derive verification plans from architecture and micro-architecture specifications, emphasizing speculative execution, pipeline hazards, and memory ordering/consistency compliance.
• Develop and maintain SystemVerilog/UVM testbenches, including agents, monitors, scoreboards, and reference models.
• Create constrained-random stimulus and directed tests targeting OoO corner cases and pipeline hazards.
• Implement self-checking mechanisms for instruction retirement, architectural state, LSU/memory ordering, atomics, and TLB/privilege flows.
• Define, track, and close functional, code, and assertion coverage gaps; add tests and monitors to improve coverage.
• Write and maintain assertions (SVA) for key micro-architectural properties and verify correctness of mispredict, exception, interrupt, flush, and data-forwarding behaviors.
• Analyze regression results, triage failures, and drive issues to closure with design and architecture teams.
• Debug complex failures (speculation/replay, load-store ordering, TLB/MMU corner cases) and collaborate with performance, modeling, and post-silicon validation teams to correlate issues.
• Contribute to DV methodology improvements and provide guidance and code reviews to junior engineers.

Requirements

Key qualifications, tools, and skills required to perform the role.

Must have:

• 5–10 years of ASIC/SoC/IP design verification experience with high-performance CPU or pipeline verification.
• Strong proficiency in SystemVerilog and UVM (or equivalent class-based DV methodology).
• Deep understanding of CPU micro-architecture: fetch/decode, rename, ROB, issue/execute, bypassing, commit, LSU, store buffer, atomics, fences, caches, and TLBs.
• Hands-on experience with constrained-random, coverage-driven verification and writing/debugging SVA assertions.
• Familiarity with industry simulators and debug tools (examples: VCS, Xcelium, Questa; Verdi/DVE or equivalent).
• Strong problem-solving, debug skills for complex corner-case bugs, and effective communication across DV, design, and architecture teams.

Nice to have:

• Experience correlating pre-silicon verification with post-silicon validation and performance/modeling teams.
• Experience improving DV methodologies, coverage strategies, and regression flows at block or subsystem scale.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.