Senior CPU Design Verification Engineer

Job Title

Senior CPU Design Verification Engineer

Role Summary

Lead block- and subsystem-level design verification for high-performance out-of-order CPU cores. Work with micro-architects and RTL designers to verify execution pipelines, memory systems, and coherence protocols using coverage-driven methodologies.

Experience Level

Senior — typically 5–10 years of ASIC/SoC/IP design verification experience, with direct experience verifying out-of-order or superscalar CPU cores or closely related high-performance pipelines.

Responsibilities

Own verification strategy, develop test environments, and drive closure of functional and coverage gaps across CPU blocks and subsystems.

• Derive and own verification plans from architecture and micro-architecture specifications, emphasizing speculative execution, pipeline hazards, and memory consistency.
• Drive verification for key OoO CPU blocks: fetch/branch prediction/decode, rename/register mapping, issue queues/schedulers, execution units, ROB/retirement/exceptions, LSU/store buffer/atomics/fences, L1 caches, TLBs, MMU and coherence interfaces.
• Develop and maintain SystemVerilog/UVM testbenches: agents, monitors, scoreboards, reference models, constrained-random stimulus, and directed tests for corner cases.
• Implement self-checking mechanisms for instruction retirement, architectural state, LSU/memory ordering, atomics, fences, and TLB/page-table/privilege flows.
• Define and track functional, code, and assertion coverage; create and maintain SVA assertions for key micro-architectural properties and close coverage gaps.
• Analyze regression results, triage failures, debug complex corner-case bugs, and drive issues to closure with design and architecture teams.
• Collaborate with performance/modeling, micro-architecture, RTL, and post-silicon validation teams to align behavior and correlate pre-/post-silicon issues.
• Contribute to DV methodology improvements and provide mentoring and code reviews for junior engineers.

Requirements

Must-have technical skills, experience, and behaviors for success in this role.

• 5–10 years of ASIC/SoC/IP design verification experience focusing on high-performance CPU pipelines.
• Direct experience verifying out-of-order or superscalar CPU cores (or closely related pipelines).
• Strong proficiency in SystemVerilog and UVM (or equivalent class-based DV methodology).
• Hands-on experience with constrained-random, coverage-driven verification and writing/debugging SVA assertions.
• Familiarity with industry simulators and debug tools (examples: VCS, Xcelium, Questa; Verdi/DVE) — experience with at least one is expected.
• Solid understanding of CPU micro-architecture: fetch/decode, rename, ROB, issue/execute, bypassing, commit; LSU, store buffer, atomics/LR-SC, fences, memory ordering; L1 caches, TLBs, and basic coherence concepts.
• Strong problem-solving and debug skills for complex, corner-case bugs; effective communication and teamwork across DV, design, and architecture teams.
• Ability to work independently on complex blocks while contributing to larger projects and mentoring junior engineers.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.