Senior Circuit Timing Engineer

Job Title

Senior Circuit Timing Engineer

Role Summary

Design, analyze, and sign off timing for custom circuit macros (digital, semi‑custom, and analog/mixed‑signal) for advanced processors. Work on transistor‑level design, timing models, and methodology as part of a global circuits team that collaborates with PD, DFX, Clocks, and other cross‑functional groups to meet power, performance, area, and reliability targets.

Experience Level

Senior. Hiring guidance: typically 6+ years of digital circuit design experience for candidates with a Master's degree or 8+ years for those with a Bachelor's degree.

Responsibilities

Primary responsibilities include timing analysis, validation, and delivery of custom circuit solutions across the design flow.

• Participate in deep‑submicron processor and custom circuit design efforts.
• Design circuits for hardware security, adaptive clocking, and power management.
• Drive timing analysis and signoff for custom macros using industry STA tools.
• Validate timing with STA and SPICE simulation tools and perform transistor‑level analysis.
• Develop timing models and methodology for novel custom macro designs.
• Perform schematic entry, transistor‑level design, and layout delivery for custom blocks.
• Integrate AI/ML techniques into design and methodology where applicable.
• Coordinate timing signoff strategy, timing constraints, convergence, DFT, and timing ECO implementation with cross‑functional teams.

Requirements

Must-have technical skills and domain experience; nice-to-have items listed where applicable.

• Must-have: Deep understanding of deep submicron process issues and digital circuit design techniques.
• Must-have: Expertise with STA tools such as Nanotime, PrimeTime, and Tempus.
• Must-have: Hands‑on experience with SPICE simulations, EM/IR analysis, and static timing analysis/closure.
• Must-have: Proven experience generating and managing timing constraints and fixing timing paths via ECOs (including crosstalk and glitch mitigation).
• Must-have: Solid understanding of extracted timing models and use of .lib files in PrimeTime.
• Must-have: Experience with process‑variation modeling and design convergence in multi‑GHz deep submicron technologies.
• Nice-to-have: Hands‑on experience in low‑power circuit techniques (power gating, decaps, multi‑Vt) and post‑silicon characterization/debug.
• Nice-to-have: Broad ownership across the silicon flow (RTL to tape‑out) and familiarity with timing closure strategies for AMS designs/IPs.

Education Requirements

Bachelor of Science in Electrical Engineering (BSEE) or Master of Science (MS) preferred in Electrical Engineering, Computer Engineering, or a closely related technical field; equivalent practical experience is accepted.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.