Senior CAD Engineer - Physical Verification

Job Title

Senior CAD Engineer - Physical Verification

Role Summary

Develop and maintain physical verification tools, flows, and methodologies to qualify memory products (DRAM, HBM, NAND, and emerging memories). Work within CAD/EDA and process teams to define signoff strategies, debug verification issues, and deliver production-ready verification solutions.

Experience Level

Senior - typically 5+ years industry experience in CAD, EDA, or semiconductor design.

Responsibilities

Accountable for rule-deck development, verification flows, and technical leadership for physical verification.

• Develop, debug, qualify, and release Calibre DRC and LVS rule decks using SVRF.
• Translate process design rules into automated verification checks and define test cases, coverage criteria, and regression strategies.
• Partner with process, design, layout, modeling, and verification teams to define signoff criteria and resolve production issues.
• Guide design teams on verification methodologies, waivers, and debugging; provide training and documentation.
• Automate verification setup, execution, and reporting; incorporate AI-assisted analysis where appropriate.
• Evaluate and adopt EDA technologies to improve verification quality, performance, and capacity.
• Lead technical projects and contribute to the physical verification roadmap.

Requirements

Must-have technical skills and experience for immediate contribution.

• 5+ years industry experience in CAD, EDA, or semiconductor design with hands-on verification work.
• Practical experience with DRC and LVS physical verification, IC layout, and process design rules.
• Ability to interpret design-rule requirements and resolve complex verification issues in production flows.
• Proficiency in Python and at least one additional scripting or programming language (SKILL, Tcl, Perl, C, or C++).
• Familiarity with Linux/Unix and shell scripting.
• Strong CMOS and VLSI fundamentals, with effective communication and debugging skills across global teams.

Nice-to-have:

• Experience developing and qualifying Calibre DRC/LVS rule decks using nmDRC, nmLVS, and RVE.
• Knowledge of layout-dependent effects, ERC/PERC, antenna, and density checks.
• Experience optimizing rule-deck coverage, runtime, and memory usage.
• Familiarity with Cadence Virtuoso, SKILL, or Cadence verification tools.
• Experience applying AI/ML or large language models to engineering workflows.
• Experience with source control, automated testing, and release management.
• Domain experience with DRAM, HBM, NAND, or emerging memory development.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.