Senior ASIC Verification Engineer — W2 Contract (100% Remote, US)

Job Title

Senior ASIC Verification Engineer — W2 Contract, 100% Remote (US)

Role Summary

Join a digital hardware team and contribute across the full silicon development lifecycle: micro-architecture, RTL development, functional verification, ASIC/FPGA/SoC implementation, and on-hardware bring-up. The role is customer-facing and requires presenting technical solutions, gathering requirements, and supporting PoC and production phases.

Experience Level

Senior-level. Years of experience not specified in the posting.

Responsibilities

Primary responsibilities include verification of high-performance compute subsystems and collaboration with cross-functional teams to drive designs to sign-off.

• Develop UVM/SystemVerilog testbenches and verification IP for compute subsystems (systolic arrays, vector/tensor datapaths, DMA, memory hierarchies).
• Define verification plans, test strategies, and coverage goals; drive closure to sign-off criteria.
• Build constrained-random and directed tests for ML datapath correctness (GEMM, convolutions, attention, mixed-precision arithmetic).
• Verify power-management behavior: clock/operand gating, power islands, DVFS transitions, idle/wake sequences, and firmware coordination.
• Create and maintain SVA assertions, scoreboards, reference models, and checkers for protocol and datapath integrity.
• Run block- and SoC-level simulation regressions and debug failures using waveforms, logs, and RTL reviews.
• Partner with RTL, architecture, firmware, and software teams for HW/SW co-verification and early emulation/FPGA bring-up.
• Contribute to low-power verification methodology and correlate pre-silicon models with post-silicon measurements.

Requirements

Key technical requirements and skills; degree requirements are listed separately below.

• Solid grounding in digital electronics, logic design, and ASIC/FPGA/SoC fundamentals.
• Hands-on experience taking designs through full lifecycle on real hardware (FPGA, SoC, or ASIC).
• Experience developing UVM/SystemVerilog testbenches and verification IP.
• Proven ability to define verification plans, coverage goals, and achieve closure.
• Experience with constrained-random verification and directed tests for ML datapaths.
• Experience writing SVA assertions, scoreboards, and reference models; strong debug skills.
• Experience verifying power-management and low-power behaviors.
• Effective collaborator with RTL, architecture, firmware, and software teams; customer-facing communication skills.
• Nice-to-have: experience with protocols and interfaces (AXI/CHI/NOC, DMA, memory interfaces) and FPGA bring-up/emulation workflows.

Education Requirements

BSc or MSc in Electronics, Radio Engineering, Computer Engineering, or a related technical field, or equivalent practical experience.

About the Company

Company: Saransh

Saransh is a staffing and engineering consulting firm that places technical contractors and specialists in roles such as ASIC/FPGA verification, hardware design, firmware, and related software integration.