Senior ASIC Verification Engineer - Remote (US)

Job Title

Senior ASIC Verification Engineer — Remote (US)

Role Summary

Join a digital hardware team to lead functional verification for high-performance compute subsystems across the full silicon lifecycle, from micro-architecture and RTL through pre-silicon verification, FPGA/ASIC bring-up, and design documentation.

The role is customer-facing: you will present technical solutions, gather requirements, support proofs-of-concept, and work with cross-functional teams (RTL, architecture, firmware, software).

Experience Level

Senior-level. The posting expects experienced engineers with proven track record taking designs through full lifecycle on real hardware; no explicit years-of-experience stated.

Responsibilities

Primary verification responsibilities include planning, implementing, and executing verification for compute datapaths and system logic.

• Develop UVM/SystemVerilog testbenches and verification IP for subsystems: systolic arrays, vector/tensor datapaths, memory hierarchies, DMA engines, and control logic.
• Define verification plans, test strategies, coverage goals (functional, code, assertion) and drive closure to sign-off criteria.
• Build constrained-random and directed tests for ML datapath correctness (GEMM, convolutions, attention, mixed-precision arithmetic, accumulation).
• Verify power-management behavior: clock/operand gating, power islands, DVFS transitions, idle/wake sequences and firmware coordination.
• Create and maintain SVA assertions, scoreboards, reference models, and checkers for protocol and datapath integrity (AXI/CHI/NOC, DMA, memory interfaces).
• Run block- and SoC-level simulation regressions; debug failures using waveforms, logs, and RTL reviews.
• Partner with RTL, architecture, firmware, and software teams on hardware–software co-verification and early emulation/FPGA bring-up.
• Contribute to low-power verification methodology: activity checks, power-state coverage, and correlation of pre-silicon models with post-silicon power measurements.

Requirements

Must-have technical skills and experience for successful performance in this role.

• Solid grounding in digital electronics, logic design, and ASIC/FPGA/SoC fundamentals.
• Proven experience taking designs through the full lifecycle on real hardware (FPGA, SoC, or ASIC).
• Hands-on UVM and SystemVerilog testbench development; experience with verification IP and test infrastructure.
• Experience writing SVA assertions, scoreboards, reference models, and protocol checkers.
• Familiarity with protocols and interfaces such as AXI, CHI, NOC, DMA, and memory interfaces.
• Strong debug skills using waveforms, simulation logs, and cross-team RTL reviews.
• Experience with low-power verification techniques and verification coverage metrics.
• Customer-facing communication skills: present technical solutions and document requirements.

Education Requirements

BSc or MSc in Electronics, Radio Engineering, Computer Engineering, Computer Science, or a related technical field (as listed in the source). No alternative "equivalent experience" statement was provided in the posting.

About the Company

Company: Oso Semiconductor

Headquarters: Mountain View, CA, United States

Early-stage fabless semiconductor startup developing mmWave beamforming RFICs that deliver 2–4x power reduction for phased array systems across SATCOM, 5G, and radar. Founded by UC Berkeley PhDs, the company has raised Series A funding and works with defense and commercial customers on full-custom mmWave front-end and beamformer chips.