Senior ASIC Verification Engineer

Job Title

Senior ASIC Verification Engineer

Role Summary

Join a digital hardware team to develop and verify ASIC/FPGA/SoC designs across the full silicon lifecycle, from micro-architecture and RTL through verification, implementation, and on-hardware bring-up. The role requires hands-on verification engineering and coordination with architecture, RTL, firmware, and software teams.

Experience Level

Senior-level. The posting does not specify a years-of-experience range.

Responsibilities

Primary verification and integration responsibilities for high-performance compute subsystems and SoC blocks.

• Develop UVM/SystemVerilog testbenches and verification IP for systolic arrays, vector/tensor datapaths, memory hierarchies, DMA engines, and control logic.
• Define verification plans, test strategies, and coverage goals (functional, code, assertion) and drive closure to sign-off criteria.
• Build constrained-random and directed tests for ML datapath correctness (GEMM, convolutions, attention, mixed-precision arithmetic, accumulation).
• Verify power-management behavior: clock/operand gating, power islands, DVFS transitions, idle/wake sequences, and firmware coordination.
• Create and maintain SVA assertions, scoreboards, reference models, and checkers for protocol and datapath integrity (AXI/CHI/NOC, DMA, memory interfaces).
• Run block- and SoC-level simulation regressions; debug failures using waveforms, logs, and cross-team RTL reviews.
• Partner with RTL, architecture, firmware, and software teams on hardware-software co-verification and early emulation/FPGA bring-up.
• Contribute to low-power verification methodology and correlate pre-silicon models with post-silicon power measurements.

Requirements

Must-have technical skills and practical experience for the role.

• Strong experience with UVM and SystemVerilog testbench development and verification IP.
• Solid grounding in digital electronics, logic design, and ASIC/FPGA/SoC fundamentals.
• Proven experience taking designs through the full lifecycle on real hardware (FPGA, SoC, or ASIC), including bring-up.
• Experience with SVA assertions, scoreboards, reference models, and protocol verification (AXI/CHI/NOC, DMA, memory interfaces).
• Skilled at running and debugging simulation regressions and conducting RTL reviews.
• Customer-facing communication: document requirements, present technical solutions, and support PoC and production phases.
• Nice-to-have: familiarity with ML datapath algorithms and mixed-precision arithmetic (GEMM, convolutions, attention).

Education Requirements

BSc or MSc in Electronics, Radio Engineering, Computer Engineering, or a related field (as listed in the source posting).

About the Company

Company: Oso Semiconductor

Headquarters: Mountain View, CA, United States

Early-stage fabless semiconductor startup developing mmWave beamforming RFICs that deliver 2–4x power reduction for phased array systems across SATCOM, 5G, and radar. Founded by UC Berkeley PhDs, the company has raised Series A funding and works with defense and commercial customers on full-custom mmWave front-end and beamformer chips.