Senior ASIC Verification Engineer

Job Title

Senior ASIC Verification Engineer

Role Summary

Join a digital hardware team responsible for verification and delivery of ASIC/SoC/FPGA designs for high-performance compute subsystems. The role covers the full silicon development lifecycle from micro‑architecture and RTL verification through FPGA/ASIC bring‑up and documentation.

Engineers are customer-facing: presenting technical solutions, gathering requirements, and supporting proof-of-concept and production phases.

Experience Level

Senior-level. Specific years of experience are not stated; role expects proven experience taking designs through real hardware lifecycle.

Responsibilities

Key responsibilities include verification planning, implementation, and integration for compute datapaths and system logic.

• Develop UVM/SystemVerilog testbenches and verification IP for compute subsystems (systolic arrays, vector/tensor datapaths, memory hierarchies, DMA, control logic).
• Define verification plans, test strategies, coverage goals (functional, code, assertion) and drive closure to sign-off.
• Build constrained-random and directed tests for ML datapath correctness (GEMM, convolutions, attention, mixed‑precision arithmetic).
• Verify low-power behavior: clock/operand gating, power islands, DVFS transitions, idle/wake sequences and firmware interactions.
• Create and maintain SVA assertions, scoreboards, reference models, and protocol/datapath checkers (AXI/CHI/NOC, DMA, memory interfaces).
• Run block- and SoC-level simulation regressions; debug failures using waveforms and logs; coordinate RTL reviews.
• Collaborate with RTL, architecture, firmware, and software teams on hardware-software co-verification and FPGA/emulation bring-up.
• Contribute to low-power verification methodology and correlate pre-silicon models with post-silicon measurements.

Requirements

Must-have technical skills and experience for effective performance in this role.

• Solid grounding in digital electronics, logic design, and ASIC/FPGA/SoC fundamentals.
• Proven experience taking a design through full lifecycle on real hardware (FPGA, SoC, or ASIC).
• Hands-on experience with UVM/SystemVerilog, verification IP, constrained-random and directed test development.
• Experience writing SVA assertions, scoreboards, and reference models; familiarity with protocol interfaces (AXI/CHI/NOC) and DMA/memory interfaces.
• Experience with simulation regressions, waveform-based debug, and cross-team RTL debugging.
• Experience with low-power verification practices and coordinating verification with firmware-controlled policies.
• Customer-facing communication: presenting technical solutions and documenting requirements.

Education Requirements

BSc or MSc in Electronics, Radio Engineering, Computer Engineering, Computer Science or a related technical field.

About the Company

Company: Oso Semiconductor

Headquarters: Mountain View, CA, United States

Early-stage fabless semiconductor startup developing mmWave beamforming RFICs that deliver 2–4x power reduction for phased array systems across SATCOM, 5G, and radar. Founded by UC Berkeley PhDs, the company has raised Series A funding and works with defense and commercial customers on full-custom mmWave front-end and beamformer chips.