Senior ASIC Verification Engineer

Job Title

Senior ASIC Verification Engineer — W2 Contract (100% Remote, US)

Role Summary

Join a digital hardware team responsible for the full silicon development lifecycle: micro-architecture, RTL, functional verification, ASIC/FPGA/SoC implementation, and on-hardware bring-up. The role requires technical ownership and frequent cross-team and customer-facing interaction to gather requirements and support PoC and production phases.

Experience Level

Senior-level. No specific years-of-experience requirement stated.

Responsibilities

Primary verification and validation responsibilities across block and SoC levels:

• Develop UVM/SystemVerilog testbenches and verification IP for high-performance compute subsystems (systolic arrays, vector/tensor datapaths, memory hierarchies, DMA engines, control logic).
• Define verification plans, test strategies, and coverage goals (functional, code, assertion); drive closure to sign-off criteria.
• Build constrained-random and directed tests for ML datapath correctness (GEMM, convolutions, attention, mixed-precision arithmetic, accumulation).
• Verify power-management behavior: clock/operand gating, power islands, DVFS transitions, idle/wake sequences, and firmware coordination.
• Create and maintain SVA assertions, scoreboards, reference models, and checkers for protocol and datapath integrity (AXI/CHI/NOC, DMA, memory interfaces).
• Run block- and SoC-level simulation regressions; debug failures using waveforms, logs, and cross-team RTL reviews.
• Partner with RTL, architecture, firmware, and software teams on hardware-software co-verification and early emulation/FPGA bring-up.
• Contribute to low-power verification methodology: activity checks, power-state coverage, and correlation of pre-silicon models with post-silicon power measurements.

Requirements

Key technical skills and practical experience required for immediate contribution:

• Must-have: Solid grounding in digital electronics, logic design, and ASIC/FPGA/SoC fundamentals.
• Must-have: Hands-on experience taking a design through the full lifecycle on real hardware (FPGA, SoC, or ASIC).
• Must-have: Experience developing UVM/SystemVerilog testbenches and verification IP.
• Must-have: Practical experience with constrained-random verification, directed tests, assertions (SVA), scoreboards, and reference models.
• Must-have: Familiarity with common interconnects and protocols (AXI/CHI/NOC), DMA and memory interface verification.
• Strong debug skills with simulators, waveforms, and regression frameworks; ability to drive cross-team debug and reviews.
• Experience with low-power verification techniques and coordination with firmware for power-state transitions.
• Effective verbal and written communication for customer-facing engineering and cross-functional collaboration.

Education Requirements

Bachelor's or Master’s degree in Electronics, Radio Engineering, Computer Engineering, Computer Science, or a related field (BSc/MSc). No explicit equivalent-experience clause provided.

About the Company

Company: Oso Semiconductor

Headquarters: Mountain View, CA, United States

Early-stage fabless semiconductor startup developing mmWave beamforming RFICs that deliver 2–4x power reduction for phased array systems across SATCOM, 5G, and radar. Founded by UC Berkeley PhDs, the company has raised Series A funding and works with defense and commercial customers on full-custom mmWave front-end and beamformer chips.