Senior ASIC Timing Engineer, DFT
NVIDIAJob Title
Senior ASIC Timing Engineer, DFT
Role Summary
Responsible for timing analysis and closure of DFT logic across NVIDIA ASICs (GPUs, CPUs, DPUs, LPUs, SoCs) at block, cluster and full-chip levels. Work closely with product design, DFX, clock and cross-functional teams to define timing strategies, constraints, convergence plans and ECO implementation.
Focus on creating robust, automated workflows and improving timing resilience and standardization.
Experience Level
Senior. Typical guidance in this posting: BS +5 years of relevant experience, or MS +2 years; equivalent practical experience may be acceptable.
Responsibilities
Primary responsibilities include:
- Drive timing analysis and closure for DFT logic at block, cluster and full-chip hierarchies.
- Develop timing constraints for custom DFT designs and ensure timing convergence across modes (scan, iJTAG, etc.).
- Collaborate with PD, DFX, Clocks and other teams to define timing closure strategy and converge on timing and power trade-offs.
- Analyze failing timing paths and implement ECOs to fix timing violations.
- Improve and automate timing workflows, add resilience and standardization to design and verification flows.
Requirements
The following are expectations for candidates. Degree details are summarized in the Education Requirements section below.
Must-have:
- Hands-on experience with Static Timing Analysis (STA) and driving timing convergence at full-chip and sub-chip levels in advanced process nodes.
- Proven experience analyzing and fixing timing paths using ECOs.
- Experience developing timing constraints for complex/custom designs.
- In-depth knowledge of industry-standard timing convergence tools and flows.
- Ability to coordinate across multiple teams to deliver timing- and power-converged designs.
Nice-to-have:
- Understanding of DFT logic and prior experience with DFT timing closure for modes such as scan and iJTAG.
- Domain experience with specialized STA and timing convergence areas (SerDes, processor cores, IO, SMVA, etc.).
- Experience in methodology or workflow development and automation for timing and DFT flows.
Education Requirements
BS (or equivalent practical experience) in Electrical or Computer Engineering with 5+ years of experience, or MS (or equivalent practical experience) with 2+ years of experience. The posting explicitly allows equivalent experience in lieu of the listed degrees.
About the Company
Company: NVIDIA
Headquarters: Santa Clara, California, USA
NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.
