Senior ASIC Timing Engineer, DFT
Lead timing analysis and closure for design-for-test (DFT) logic across GPU/CPU/DPU/SoC projects at block, cluster, and full-chip levels. Collaborate with product design, DFX, clocking, and other teams to define timing strategies, close timing and power targets, and implement ECOs. Drive automation and standardization of timing workflows.
Senior-level. Experience guidance: BS in Electrical or Computer Engineering with 5+ years, or MS with 2+ years (or equivalent practical experience).
Primary day-to-day responsibilities include:
Must-have technical skills and experience:
Nice-to-have:
Bachelor's degree in Electrical Engineering or Computer Engineering (BS) with 5+ years of relevant experience, or a Master’s degree (MS) with 2+ years of relevant experience. Equivalent practical experience is explicitly accepted.
Company: NVIDIA
Headquarters: Santa Clara, California, USA
NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.
