Senior ASIC Timing Engineer

Job Title

Senior ASIC Timing Engineer

Role Summary

Lead timing analysis and closure for NVIDIA ASICs (GPUs, CPUs, LPUs, SoCs) across block, cluster, and full-chip scopes. Work with RTL, DFX, clocks, physical design, and methodology teams to define constraints, drive convergence, and implement ECOs.

Short, technical role focused on achieving timing and power convergence for advanced process nodes.

Experience Level

Senior. Typical experience: 3–5+ years in static timing analysis and timing closure (senior-level expectations apply).

Responsibilities

The role centers on driving timing closure and collaborating with cross-functional teams to deliver tapeouts.

• Lead block-level, cluster-level, and full-chip static timing analysis and closure efforts.
• Create and manage timing constraints and closure strategies with RTL, clocks, and DFX teams.
• Analyze and fix timing paths via ECOs; perform crosstalk and noise analysis as required.
• Work with physical-design teams on synthesis, placement, routing, and logic restructuring to improve timing and power.
• Improve timing convergence flows in collaboration with methodology and automation teams.
• Support timing sign-off and verification across modes (e.g., different operating modes or test modes).

Requirements

Must-have technical skills and domain experience.

• Hands-on experience with full-chip and sub-chip static timing analysis (STA) and timing convergence.
• Experience generating and managing timing constraints and performing convergence at scale.
• Proven ability to analyze and correct timing failures using ECOs; familiarity with crosstalk and noise effects.
• Practical experience with physical-design optimization techniques (synthesis, placement, routing, logic restructuring).
• In-depth knowledge of industry-standard STA and timing-convergence tools.
• Experience modeling and converging timing for deep sub-micron process nodes.

Nice-to-have:

• Domain-specific STA experience for GPUs, CPUs, LPUs, or SoCs.
• Background in logic synthesis, equivalence checking, or formal verification.
• Experience with DFT timing closure (scan, BIST, etc.) and AMS digital macro timing.
• Methodology and flow development experience, including automation.

Education Requirements

BS in Electrical or Computer Engineering (or equivalent practical experience) with ~5 years in timing/STA, or MS with ~3 years in timing/STA. Equivalent practical experience in timing and STA is accepted.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.