Senior ASIC RTL Design Engineer

Job Title

Senior ASIC RTL Design Engineer

Role Summary

Responsible for RTL design and integration of high-speed interfaces and IP for ASIC projects. Work includes Verilog RTL coding, logic synthesis, timing constraints, and implementing forward error correction and BER analysis.

This is a 12+ month contract role based in Boston, MA, starting in September, embedded in the ASIC design team collaborating with verification, synthesis, and physical design engineers.

Experience Level

Senior-level. Specific years of experience not stated.

Responsibilities

Core responsibilities include:

• Develop and maintain Verilog RTL for ASIC blocks and subsystems.
• Define and apply timing constraints; support logic synthesis and timing closure.
• Design and integrate high-speed memory and interface controllers (e.g., LPDDR, UFS, PCIe).
• Implement and validate Forward Error Correction (FEC) and perform BER calculations.
• Integrate soft IP (industry-standard and custom) and calculate bandwidth requirements.
• Collaborate with verification, physical design, and system teams to meet performance and area targets.
• Produce design documentation and support reviews.

Requirements

Must-have technical skills:

• Proven senior ASIC RTL design experience.
• Strong Verilog RTL coding skills.
• Experience with high-speed memory interfaces and controllers.
• Experience with logic synthesis and creating/tuning timing constraints.
• Knowledge of FEC and BER analysis.
• Experience integrating soft IP and performing bandwidth calculations.

Nice-to-have:

• Experience with LPDDR5, UFS/Flash, and PCIe Gen4/5.

Education Requirements

Not specified.

About the Company

Company: INFT Solutions

Provides engineering staffing and contract services for semiconductor and electronics companies, including design, verification, and test support such as DFT and ATPG expertise.