Senior ASIC RTL Design Engineer

Job Title

Senior ASIC RTL Design Engineer

Role Summary

Senior engineer joining a digital hardware team to deliver RTL for high-performance compute subsystems across the full silicon lifecycle. Work includes architecture translation, RTL development, verification/FPGA bring-up, power optimization, and post-silicon debug.

Customer-facing role on a W2 contract, 100% remote within the United States.

Experience Level

Senior-level. Years of experience not specified in the source.

Responsibilities

Key responsibilities include:

• Design synthesizable SystemVerilog/Verilog for compute subsystems (systolic arrays, vector/tensor datapaths, on-chip memory, DMA engines, control logic).
• Translate architecture specifications into PPA-efficient RTL; drive timing closure and hand off to synthesis, physical design, and verification teams.
• Investigate and implement power optimizations (clock gating, operand gating, power islands, voltage domains, datapath activity reduction).
• Build and refine RTL-level power models and collaborate on power budgeting and measurement correlation through pre- and post-silicon milestones.
• Define and integrate chip-wide power management strategies (DVFS, idle/sleep states, wake sequencing) and coordinate with firmware and thermal policies.
• Integrate blocks at SoC/top level — manage clock/reset domains, bus fabrics (AXI/CHI/NOC), and DFT; apply low-power design methodology (lint, CDC/RDC, synthesis constraints).
• Partner with architects, physical design, verification, firmware, and compiler/runtime teams on hardware–software co-design and ML kernel mapping.
• Support FPGA/emulation bring-up and post-silicon debug; analyze waveforms, evaluate power/performance trade-offs, and propose ECOs.
• Present technical solutions and gather/document customer requirements; support PoC and production phases.

Requirements

Must-have technical skills and experience:

• Strong grounding in digital electronics, logic design, and ASIC/FPGA/SoC fundamentals.
• Proven experience taking designs through the full lifecycle on real hardware (FPGA, SoC, or ASIC).
• Proficiency in RTL design (SystemVerilog/Verilog) for high-performance datapaths.
• Experience with low-power design techniques and RTL-level power modeling.
• Scripting proficiency (Python, Tcl) for automation and debug.
• Familiarity with industry EDA flows and tools (e.g., DC/Genus, PrimeTime, VCS/Xcelium, SpyGlass, Verdi).
• Strong ownership, problem-solving, and verbal/written communication skills for customer-facing interactions.

Education Requirements

BSc or MSc in Electronics, Radio Engineering, Computer Engineering, or a related field is required per the posting.

About the Company

Company: INFT Solutions

Provides engineering staffing and contract services for semiconductor and electronics companies, including design, verification, and test support such as DFT and ATPG expertise.