Senior ASIC Power Management Micro Architect, Chip Design
As a Senior ASIC Power Management Micro Architect on the Chip Design team you will own front-end micro-architecture and RTL development for Power Management IP and lead the block through design, tape-out, and post-silicon bring-up.
Collaborate with architecture, verification, physical design, and validation teams to deliver production silicon and enable new power-management technologies across product lines.
Senior β typically 12+ years of hands-on RTL and ASIC design experience.
Primary responsibilities include micro-architecture definition, RTL delivery, and post-silicon enablement for Power Management IP.
Must-have skills and experience; nice-to-have items listed at the end.
Bachelor's (BSc) or Master's (MSc) in Electrical Engineering, Computer Engineering, or a related field β or equivalent practical experience.
Company: NVIDIA
Headquarters: Santa Clara, California, USA
NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.
