Senior ASIC Power Delivery Engineer

Job Title

Senior ASIC Power Delivery Engineer

Role Summary

Join a hardware team focused on AI/ML acceleration to lead power-delivery architecture and implementation for advanced ASICs. The role drives PDN design, verification, and integration across advanced process nodes and 3D-stacked designs.

Work cross-functionally with architecture, physical design, packaging, and verification teams to ensure robust power integrity and meet project milestones.

Experience Level

Senior — requires substantial experience; the posting specifies 8+ years of relevant technical experience.

Responsibilities

Core responsibilities include PDN architecture, design, verification, and cross-team integration for advanced ASIC projects.

• Perform early process and metal-stack analysis to influence power architecture choices.
• Deliver power grid designs for all power domains meeting density and integration constraints.
• Optimize through-silicon via (TSV) and power-grid co-design for 3D-stacked dies; ensure DRC cleanliness and electromigration robustness.
• Collaborate with architecture, floorplanning, P&R, and packaging teams to co-optimize designs and accommodate top-level routing.
• Stabilize and finalize power-grid designs to meet project milestones and tapeout schedules.
• Perform power-budgeting, IR-drop and electromigration analysis, verification, and signoff activities.

Requirements

Must-have technical skills and practical experience to execute the responsibilities above.

• Must-have: 8+ years of technical experience in physical design disciplines focused on power delivery and advanced process technology nodes.
• Must-have: Hands-on experience with power-grid integrity: budgeting, IR-drop and electromigration analysis, verification, and signoff.
• Must-have: Familiarity with place-and-route flows and tools, electromigration/IR-drop tools, and DRC tools.
• Must-have: Experience with 3D-stacked die PDN co-design and TSV optimization.
• Must-have: Strong cross-functional collaboration and communication skills.
• Nice-to-have: Ownership experience for power-grid design and close collaboration with architecture owners.
• Nice-to-have: Knowledge of voltage budgeting and drop-mitigation strategies for new projects.
• Nice-to-have: Familiarity with low-power techniques such as Unified Power Format (UPF) and dynamic voltage and frequency scaling (DVFS).

Education Requirements

Required: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. Preferred: Master's or PhD in a relevant field (computer architecture emphasis noted). The posting explicitly allows equivalent practical experience in lieu of a degree.

About the Company

Company: Google

Headquarters: Mountain View, CA, United States

Google is a global technology company that develops Internet services and products including search, advertising, cloud computing, AI, software, hardware, and custom silicon for consumer and enterprise applications.