Senior ASIC Physical Design Engineering Technical Lead

Job Title

Senior ASIC Physical Design Engineering Technical Lead

Role Summary

Lead full-chip physical design and implementation efforts for advanced-node ASICs, driving floorplan, timing closure, power integrity, and sign-off methodologies. Work closely with RTL, DFT, package, system, foundry, IP vendors and EDA tool teams to optimize performance, power, and die size.

Experience Level

Senior-level role. See Education Requirements for the role-specific experience expectations tied to degree level.

Responsibilities

Own and execute full-chip physical design and implementation activities.

• Create and validate full-chip floorplans incorporating architecture, foundry guidelines, IP placement and package constraints.
• Perform hierarchical implementation: partitioning, pin assignment, clock planning, bump planning, and hierarchical timing closure.
• Drive RTL-to-GDSII flow: floorplan, power-grid planning, place-and-route, static timing analysis, power integrity, physical verification and equivalence checks.
• Design and implement full-chip clock strategies (mesh, H-tree/Flex-HTree) and low-power methodologies (UPF).
• Analyze existing tool flows and introduce efficiency or methodology improvements; collaborate with EDA vendors and internal tool teams.
• Coordinate with foundry and standard-cell/IP vendors to define signoff methodologies and address post-silicon validation feedback.
• Apply AI-assisted tools and scripting to boost productivity and automation of flows.

Requirements

Must-have technical skills and domain experience.

• Significant ASIC physical-design experience with full RTL-to-GDSII project delivery in advanced process nodes (7nm/5nm/3nm or below).
• Hands-on experience with EDA implementation and analysis tools such as Innovus, Tempus/PrimeTime, RedHawk/Voltus, Calibre or Pegasus.
• Practical expertise in floorplanning, power-grid planning, place-and-route, static timing analysis, and power integrity analysis.
• Experience defining clock architectures at chip level (mesh, H-tree) and implementing signoff-quality timing closure techniques.
• Experience collaborating with RTL, DFT, implementation teams, foundry and IP vendors to drive signoff and manufacturing readiness.
• Familiarity with low-power design methodologies and UPF flows.
• Ability to analyze and improve tool flows and automation; proficiency with scripting and tool integration.

Nice-to-have:

• Experience with hierarchical design flows, partitioning and pin-assignment at full-chip scale.
• Python scripting and demonstrated use of AI tools for productivity and flow automation.
• Experience receiving and incorporating post-silicon validation feedback.

Education Requirements

Minimum Qualifications state: Bachelor's degree in Electrical Engineering with 12+ years of Physical Design experience; OR Master's degree in Electrical Engineering with 8+ years of Physical Design experience; OR PhD in Electrical Engineering with 5+ years of Physical Design experience. Field specified: Electrical Engineering. (No alternative degree fields or certifications were listed.)

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).