Senior ASIC Physical Design Engineering Technical Lead

Job Title

Senior ASIC Physical Design Engineering Technical Lead

Role Summary

Lead full-chip physical design and implementation for advanced-node ASICs, focusing on floorplanning, power and clock planning, place-and-route, timing and power signoff. Collaborate with RTL, DFT, package, foundry, IP vendors and EDA tool teams to deliver optimized tapeouts.

Drive methodology and flow improvements to meet performance, power and die-size targets on advanced process nodes.

Experience Level

Senior — substantial ASIC physical-design leadership experience expected. Typical experience guidance from the posting: PhD: 5+ years; Master's: 8+ years; Bachelor's: 12+ years.

Responsibilities

Primary responsibilities include leading full-chip implementation and improving tool flows and methodologies.

• Create full-chip floorplans considering architecture, IP placement and foundry integration guidelines.
• Collaborate with system and package teams to incorporate requirements into the full-chip floorplan.
• Perform hierarchical implementation: partitioning, pin assignment, clock planning and bump planning; implement full-chip clock mesh and Flex-HTree methods.
• Execute RTL-to-GDSII flow: floorplan, power-grid planning, place-and-route, static timing analysis, power integrity, physical verification and equivalence checking.
• Optimize designs for performance, power and die size across implementation stages.
• Analyze existing tool flows, identify efficiency gaps and implement incremental or transformative enhancements.
• Work closely with RTL, DFT, implementation teams and EDA vendors to enable best-in-class design methodology.
• Define signoff methodologies with foundry and standard-cell/IP vendors and validate/adjust them after post-silicon feedback.
• Apply low-power design methodologies using UPF and leverage AI tools to improve productivity.

Requirements

Must-have technical skills and domain experience.

• Proven RTL-to-GDSII implementation experience and tapeouts at 7nm/5nm/3nm or below process nodes.
• Experience with EDA tools such as Cadence Innovus, Synopsys Tempus/PrimeTime, Redhawk/Voltus and Mentor/Calibre or Siemens Pegasus.
• Hands-on experience with full-chip floorplanning, power-grid planning, partitioning and pin-assignment.
• Experience with hierarchical design flows, timing closure, static timing analysis, corners/voltage definitions and power integrity analysis.
• Expertise in chip-level clocking (H-Tree, mesh) and clock mesh/Flex-HTree implementations.
• Proficiency with low-power methodologies (UPF) and power-integrity signoff practices.
• Familiarity with Python for automation and experience using AI tools to improve productivity.
• Experience collaborating with foundry and IP vendors on signoff methodologies and validation.

Education Requirements

Bachelor's Degree in Electrical Engineering with 12+ years of physical-design experience; or Master's Degree in Electrical Engineering with 8+ years; or PhD in Electrical Engineering with 5+ years. Field specified: Electrical Engineering.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).