Senior ASIC Physical Design Engineering Technical Lead

Job Title

Senior ASIC Physical Design Engineering Technical Lead

Role Summary

Lead physical-design engineering for full-chip implementation and signoff on advanced-node ASICs. Work across architecture, RTL, package, and foundry teams to produce optimized floorplans, power grids, clocking, and final tapeouts with a focus on performance, power, and die size.

Experience Level

Senior-level. Required experience varies by degree: PhD with 5+ years physical design experience, Master's with 8+ years, or Bachelor's with 12+ years.

Responsibilities

Primary technical and leadership responsibilities for full-chip physical implementation and methodology improvements.

• Define and implement full-chip floorplans integrating architecture, IP placement, and foundry constraints.
• Collaborate with system, package, RTL, DFT, and post-silicon validation teams to meet design requirements.
• Execute hierarchical implementation flows: partitioning, pin assignment, bump planning, and clock planning (mesh and Flex-HTree techniques).
• Drive RTL-to-GDSII flow: floorplan, power grid, place-and-route, STA, power integrity, physical verification, and equivalence checks.
• Work with foundry and standard-cell/IP vendors to define and validate signoff methodologies.
• Analyze and improve EDA tool flows and design methodology for efficiency and quality.
• Mentor engineers and coordinate with EDA vendors and tool/flow teams to enable best-in-class methodologies.
• Apply AI-assisted tools to improve productivity and automation where appropriate.

Requirements

Must-have technical skills and relevant experience for the role; preferred items listed where applicable.

• Must-have: Extensive physical-design experience with RTL-to-GDSII flow and tapeouts in advanced process nodes (7nm/5nm/3nm or below).
• Must-have: Hands-on experience with full-chip floorplanning, power-grid planning, partitioning, and pin-assignment.
• Must-have: Proficiency with EDA tools such as Innovus, Tempus/PrimeTime, RedHawk/Voltus, and Calibre/Pegasus.
• Must-have: Strong static timing analysis, timing-closure, corner/voltage methodologies, and power-integrity analysis skills.
• Must-have: Experience implementing chip-level clocking strategies (H-Tree, mesh) and low-power design methodologies (UPF).
• Preferred: Experience working on full-chip activities in hierarchical designs and integrating post-silicon feedback into signoff flows.
• Preferred: Python scripting and demonstrated use of AI tools for design automation and productivity.

Education Requirements

Degree in Electrical Engineering: Bachelor's degree with 12+ years of physical-design experience, Master's degree with 8+ years, or PhD with 5+ years. (Source lists Electrical Engineering specifically.)

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).