Senior ASIC Physical Design Engineering Technical Lead

Job Title

Senior ASIC Physical Design Engineering Technical Lead

Role Summary

Lead physical implementation and full-chip floorplanning for high-performance ASIC designs. Work across RTL, DFT, implementation, EDA vendors, foundry and IP partners to deliver RTL-to-GDSII tapeouts focused on performance, power and die-size optimization.

Drive methodology and flow improvements, mentor engineers, and coordinate cross-team integration for complex advanced-node designs.

Experience Level

Senior. Candidates will typically meet one of the degree+experience combinations listed in Education Requirements (Bachelor's +12 years, Master's +8 years, PhD +5 years) and have extensive physical design and tapeout experience.

Responsibilities

Deliver and own full-chip physical design activities from floorplan through signoff, and improve tool flows and methodologies.

• Create full-chip floorplans that incorporate architecture, IP placement, package and foundry constraints.
• Perform hierarchical implementation: partitioning, pin assignment, clock planning, bump planning, and power-grid planning.
• Implement RTL-to-GDSII flow: place-and-route, static timing analysis, power integrity analysis, physical verification and equivalence checks.
• Design and validate chip-level clocking strategies (clock mesh, H-Tree/Flex-HTree).
• Optimize designs for performance, power, and die area; manage corners and voltage definitions for signoff.
• Collaborate with RTL, DFT, validation, EDA vendors, foundry and IP partners to define and validate signoff methodologies.
• Analyze existing tool flows, identify gaps, and implement incremental or transformative improvements.

Requirements

Key technical skills and domain experience required for successful performance in this role.

• Must-have: Hands-on experience with RTL-to-GDSII flow and delivery of tapeouts in advanced process technologies (7nm/5nm/3nm or below).
• Proven use of physical design and EDA toolsets such as Cadence Innovus, Synopsys Tempus/PrimeTime, Redhawk/Voltus, and Mentor Calibre/Pegasus.
• Strong experience in full-chip floorplanning, power-grid planning, partitioning, pin-assignment, place-and-route, STA, and power integrity analysis.
• Practical experience with chip-level clock architectures (mesh and H-Tree) and low-power methodologies (UPF).
• Experience working directly with foundry and standard-cell/IP vendors to define signoff flows and address post-silicon feedback.
• Nice-to-have: Familiarity with Python for flow automation and demonstrated use of AI tools to improve productivity.

Education Requirements

Degree in Electrical Engineering: Bachelor's degree with 12+ years of physical design experience, Master's degree with 8+ years, or PhD with 5+ years. No specific certifications were listed.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).