Senior ASIC Physical Design Engineer (requires security clearance)

Job Title

Senior ASIC Physical Design Engineer (requires security clearance)

Role Summary

Join the Miniature Device Technologies Group to lead back-end physical design for custom ASICs used in miniature, low-power systems for national security applications. Work across digital, mixed-signal, and custom blocks to deliver tapeout-ready layouts and drive process and design decisions for new proposals.

Experience Level

Senior — requires substantial independent experience; this role specifies 6 years of back-end ASIC design experience.

Responsibilities

The core responsibility is full digital back-end flow and top-level physical completion. Key duties include:

• Implement digital back-end flow from synthesis through a completed, verified top-level layout ready for tapeout.
• Floorplan top-level digital and mixed-signal ASIC layouts and partition designs to meet timing and area goals.
• Perform static timing analysis, timing closure, and design partitioning across RTL and gate-level phases.
• Insert SCAN and BIST to maximize test/defect coverage and support testability.
• Execute physical verification and signoff checks (DRC, LVS, mask checks and related verification).
• Perform custom physical layout and top-level custom modifications when required.
• Evaluate process options for proposals, including technology trade-offs for size, power, features, and IP availability.
• Debug back-end issues with digital designers at RTL and gate level and implement fixes.
• Contribute to EDA environment improvements, scripting, and automation to streamline flows.
• Provide technical leadership and mentoring to junior physical design engineers and collaborate with cross-functional teams.

Requirements

Must-have skills, security and experience requirements are listed below. Nice-to-have items follow.

• Must-have: Skilled with Cadence ASIC back-end design tools for implementation and flow.
• Skilled with Siemens Calibre for physical verification and signoff.
• Minimum 6 years of hands-on back-end ASIC design experience.
• Ability to obtain an Interim Secret clearance by start date and ultimately a Secret clearance; U.S. citizenship is required.
• Experience with timing analysis, floorplanning, SCAN/BIST insertion, physical verification, and tapeout processes.
• Strong debugging skills across RTL and gate-level issues related to back-end implementation.
• Nice-to-have: Experience with custom layout in Cadence Virtuoso and familiarity with Siemens ASIC implementation tools.
• Experience in ASIC technology characterization and process selection for size/power/IP trade-offs.
• Active security clearance or prior successful single-scope background investigation is advantageous.

Education Requirements

Associate's degree in a technical field, or an equivalent combination of education, experience, and/or certifications is acceptable; equivalent practical experience is explicitly noted as acceptable.

About the Company

Company: Johns Hopkins Applied Physics Laboratory

Headquarters: Laurel, Maryland, United States

Johns Hopkins Applied Physics Laboratory is a nonprofit, university-affiliated research center that develops advanced engineering, science, and technology solutions for national security, space, and government-sponsored missions.