Senior ASIC Physical Design Engineer (Requires Security Clearance)

Job Title

Senior ASIC Physical Design Engineer (Requires Security Clearance)

Role Summary

Join the Miniature Device Technologies Group to lead digital back-end and physical layout for custom ASICs used in national-security applications. The role focuses on synthesis through tapeout of top-level digital and mixed-signal layouts, physical verification, and process selection for small, low-power systems.

Salary range: $105,000–$290,000 annually.

Experience Level

Senior — requires demonstrated back-end ASIC design experience; posting specifies 6 years performing back-end ASIC design.

Responsibilities

Primary responsibilities center on ASIC digital back-end and top-level physical implementation.

• Execute digital back-end flow from synthesis to a verified, tapeout-ready top-level layout.
• Floorplan top-level digital and mixed-signal ASICs and perform design partitioning to meet timing.
• Perform timing analysis, constraint generation, and timing closure activities.
• Insert SCAN and BIST for test coverage and support DFT strategies.
• Perform physical verification, including DRC, MCD and LVS checks.
• Perform custom physical layout and top-level custom modifications as required.
• Debug back-end related RTL and gate-level issues in collaboration with digital designers.
• Support process selection and technology characterization for proposals and designs.
• Contribute to tool environment improvements and scripting; mentor junior physical designers.

Requirements

Must-have technical skills, clearance eligibility, and experience.

• Skilled with Cadence ASIC back-end tools for implementation (synthesis, place and route, signoff flows).
• Skilled with Siemens Calibre (physical verification) tools.
• Minimum 6 years of hands-on back-end ASIC design experience.
• Able to obtain an Interim Secret clearance by start date and ultimately obtain a Secret clearance; U.S. citizenship required.
• Experience debugging RTL and gate-level issues related to physical design.

Nice-to-have:

• Experience with Cadence Virtuoso custom layout.
• Familiarity with Siemens back-end toolset beyond Calibre and with ASIC technology characterization.
• Existing active security clearance or prior Single Scope Background Investigation (SSBI).

Education Requirements

Associate's degree in a technical field OR equivalent combination of education, certifications, and practical experience. Equivalent practical experience is acceptable per the posting.

About the Company

Company: Johns Hopkins Applied Physics Laboratory

Headquarters: Laurel, Maryland, United States

Johns Hopkins Applied Physics Laboratory is a nonprofit, university-affiliated research center that develops advanced engineering, science, and technology solutions for national security, space, and government-sponsored missions.