Senior ASIC Physical Design Engineer, Netlisting

Job Title

Senior ASIC Physical Design Engineer, Netlisting

Role Summary

Drive physical-design activities for high-frequency and low-power CPUs, GPUs and SoCs at block, cluster, and full-chip levels with a primary focus on netlist-related flows: equivalence checking, clock-domain-crossing checks, MTBF analysis, logic synthesis, and netlist quality. Work within the physical design team and collaborate with RTL designers, verification, and tooling groups to achieve timing closure and tapeout-ready netlists.

Experience Level

Senior. Expect an experienced engineer with multiple years of hands-on physical-design and netlist verification experience (guidance: 5+ years or equivalent practical experience).

Responsibilities

Key responsibilities include driving netlist quality and timing closure across design scopes and supporting flow development and ECO implementation.

• Drive netlist-focused physical design tasks: equivalence checking (RTL-to-tapeout), netlist quality checks, and asynchronous/CDC checks including MTBF analysis.
• Lead timing convergence efforts: static timing analysis (full-chip and sub-chip), timing constraints generation and management.
• Perform and guide logic synthesis work at block or full-chip level and support synthesis flow development.
• Create and implement ECOs and support late-stage fixes to meet timing and layout requirements.
• Develop, maintain, and apply EDA tool flows and in-house tooling for netlist validation and signoff.
• Automate tasks and integrate scripts into flows to improve productivity and reproducibility.
• Collaborate with architects, RTL designers, verification, DFT, and CAD teams to resolve cross-domain issues and drive tapeout readiness.

Requirements

Must-have technical skills and practical experience.

• Must-have: Expertise in logic equivalence checking and formal verification workflows from RTL to tapeout using industry-standard tools.
• Must-have: Strong hands-on experience in static timing analysis, timing constraints generation/management, and timing convergence.
• Must-have: Experience with clock-domain-crossing checking and MTBF analysis (industry or in-house tools).
• Must-have: Practical experience with logic synthesis at block or full-chip level and associated flow execution.
• Must-have: Proficiency in scripting and automation (Perl, TCL, Make, Python, or similar).
• Must-have: Deep familiarity with industry-standard EDA tools relevant to physical design and verification.
• Nice-to-have: Background in DFT timing closure (scan shift/capture, transition faults, BIST) and experience improving workflows via automation or AI-assisted tooling.
• Nice-to-have: Strong debugging skills and a track record of improving productivity and tooling.

Education Requirements

BS in Electrical Engineering or Computer Engineering with 5+ years' experience, or MS with 3+ years' experience; equivalent practical experience is acceptable. Relevant fields include Electrical Engineering, Computer Engineering, or closely related technical disciplines.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.