Senior ASIC Physical Design Engineer

Job Title

Senior ASIC Physical Design Engineer

Role Summary

Senior engineer responsible for ASIC physical implementation, timing analysis and signoff for high-performance integrated circuits. Work with ASIC design, physical implementation, DFT, signal integrity, architecture and cross-functional teams to deliver physically aware designs and scalable methodologies.

This position is hybrid with an average requirement of approximately 2 days per week in an HPE office; locations include Ft. Collins, CO and Chippewa Falls, WI.

Experience Level

Senior - typically 6–10 years of professional experience in ASIC, VLSI, or semiconductor design implementation, with strong physical-design and timing-closure background.

Responsibilities

Accountable for timing and physical design activities from partition-level to full-chip signoff and for improving implementation flows.

• Perform static timing analysis for hierarchical and full-chip designs; create and validate timing constraints and budgets.
• Drive timing closure (setup, hold, clock, I/O, test) and analyze/resolve critical paths.
• Perform synthesis, netlist quality checks, and formal verification tasks.
• Support chip partitioning, floorplanning and physical implementation work.
• Create and manage engineering change orders (ECOs) and implement fixes affecting performance, power, and area.
• Develop and maintain flow automation and methodology improvements (scripting, tool flows, signoff flows).
• Collaborate with cross-functional teams to align architecture and implementation with physical design constraints.
• Review designs for compliance with ASIC technology and methodology standards.
• Provide technical guidance and mentoring to less-experienced engineers.

Requirements

Must-have technical skills and experience; preferred items listed where applicable.

• Typically 6–10 years of experience in ASIC/VLSI physical design and timing closure.
• Strong understanding of digital logic, VLSI principles, circuit design, and computer architecture.
• Hands-on experience with static timing analysis, timing signoff, and timing-constraint development.
• Experience with synthesis, netlist quality analysis, formal verification, ECO implementation, floorplanning and partitioning.
• Proficiency with industry EDA tools (examples: Synopsys Fusion Compiler, Design Compiler, PrimeTime, Formality; Cadence Genus/RTL Compiler/LEC).
• Scripting and automation skills using Perl, Python, Tcl, or similar languages.
• Strong analytical, debugging and communication skills; able to work independently and in cross-disciplinary teams.
• Nice-to-have: experience developing implementation flows and automation, hierarchical timing analysis, full-chip timing closure, advanced-node process experience, and prior mentorship/technical leadership.
• Nice-to-have: publications, patents, or other contributions in ASIC/VLSI/physical design or EDA.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, Microelectronics, or a related technical field. A Master’s degree or graduate coursework is listed as preferred.

Additional Information

Salary range (Colorado, United States): USD 147,000 - 279,000 annual base. Variable incentives may also be offered. HPE supports workplace accessibility; applicants who need accommodation can request assistance via the company's secure candidate support form: https://people.hpe.com/s/externalcase/candidate-support.

About the Company

Company: Hewlett Packard Enterprise

Headquarters: Spring, TX, United States

Global enterprise technology company delivering hybrid cloud, edge-to-cloud platforms, servers, storage, networking, and IT services to help organizations build, run, and secure applications and infrastructure at scale.