Senior ASIC Physical Design Engineer

Job Title

Senior ASIC Physical Design Engineer

Role Summary

Senior engineer responsible for digital back-end (physical) ASIC implementation from synthesis through a verified top-level layout ready for tapeout. Work includes floorplanning, timing analysis and closure, SCAN/BIST insertion, physical verification, and custom physical layout as required.

Member of the Miniature Device Technologies Group collaborating with digital designers, verification, and software teams to deliver ultra-small, low-power ASIC solutions for national-security applications.

Experience Level

Senior-level. Requires at least 6 years of hands-on back-end ASIC design experience.

Responsibilities

Primary responsibilities focus on back-end ASIC physical design and verification.

• Implement full digital back-end flow from synthesis to completed top-level layout for tapeout.
• Top-level floorplanning for digital and mixed-signal ASICs and partitioning to meet timing and area goals.
• Perform static timing analysis and drive timing closure across RTL and gate-level phases.
• Insert SCAN and BIST to maximize defect coverage.
• Execute physical verification (DRC, MRC/DRC+, MCD, LVS) and resolve violations.
• Perform custom physical layout and top-level custom modifications as needed.
• Investigate and recommend process selection and technology trade-offs for proposals and designs.
• Debug back-end issues in collaboration with digital designers and verification teams.
• Drive process improvements, tooling/scripting enhancements, and automation for the ASIC environment.
• Provide technical leadership and mentorship to junior physical design engineers and coordinate cross-functional project work.

Requirements

Must-have technical skills, security, and experience.

• 6+ years performing back-end ASIC physical design.
• Proficient with Cadence ASIC back-end toolset for implementation and physical design flows.
• Proficient with Siemens Calibre for physical verification (DRC/LVS/MCD/DRC+).
• Hands-on experience with synthesis, floorplanning, timing analysis, SCAN/BIST insertion, and physical verification flows.
• Ability to obtain an Interim Secret security clearance by start date and ultimately a Secret clearance; U.S. citizenship required.

Nice-to-have:

• Experience with custom physical layout in Cadence Virtuoso.
• Experience with Siemens ASIC implementation tools beyond Calibre.
• Experience in ASIC technology characterization and process selection.
• Active security clearance or prior successful single-scope background investigation.

Education Requirements

Associate's degree in a technical field, or an equivalent combination of education, certifications, and practical experience.

About the Company

Company: Johns Hopkins Applied Physics Laboratory

Headquarters: Laurel, Maryland, United States

Johns Hopkins Applied Physics Laboratory is a nonprofit, university-affiliated research center that develops advanced engineering, science, and technology solutions for national security, space, and government-sponsored missions.